241 lines
15 KiB
Plaintext
241 lines
15 KiB
Plaintext
----------------------------------------------------------------
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| Motorola |
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| 666 88888 000 5555555 |
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| 6 8 8 0 0 5 |
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| 6 8 8 0 0 0 5 |
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| 666666 88888 0 0 0 555555 |
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| 6 6 8 8 0 0 0 5 |
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| 6 6 8 8 0 0 5 |
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| 66666 88888 000 555555 |
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| 6805 MICROPROCESSOR Instruction Set Summary |
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| _________ _________ |
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| _| \__/ |_ |
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| Vss |_|1 40|_| PA7 <--> |
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| _____ _| |_ |
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| --> RESET |_|2 39|_| PA6 <--> |
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| ___ _| |_ |
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| --> INT |_|3 38|_| PA5 <--> |
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| _| |_ |
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| Vcc |_|4 37|_| PA4 <--> |
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| _| |_ |
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| --> EXTAL |_|5 36|_| PA3 <--> |
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| _| |_ |
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| --> XTAL |_|6 35|_| PA2 <--> |
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| _| |_ |
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| NUM |_|7 34|_| PA1 <--> |
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| _| |_ |
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| --> TIMER |_|8 33|_| PA0 <--> |
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| _| |_ |
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| <--> PC0 |_|9 32|_| PB7 <--> |
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| _| |_ |
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| <--> PC1 |_|10 MC6805U2 31|_| PB6 <--> |
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| _| |_ |
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| <--> PC2 |_|11 30|_| PB5 <--> |
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| _| |_ |
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| <--> PC3 |_|12 29|_| PB4 <--> |
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| _| |_ |
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| <--> PC4 |_|13 28|_| PB3 <--> |
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| _| |_ |
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| <--> PC5 |_|14 27|_| PB2 <--> |
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| _| |_ |
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| <--> PC6 |_|15 26|_| PB1 <--> |
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| _| |_ |
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| <--> PC7 |_|16 25|_| PB0 <--> |
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| _| |_ |
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| <--> PD7 |_|17 24|_| PD0 <--> |
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| ____ _| |_ |
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| <--> PD6/INT2 |_|18 23|_| PD1 <--> |
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| _| |_ |
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| <--> PD5 |_|19 22|_| PD2 <--> |
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| _| |_ |
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| <--> PD4 |_|20 21|_| PD3 <--> |
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| |______________________| |
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|Written by Jonathan Bowen |
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| Programming Research Group |
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| Oxford University Computing Laboratory |
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| 8-11 Keble Road |
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| Oxford OX1 3QD |
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| England |
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| Tel +44-865-273840 |
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|Created August 1981 |
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|Updated April 1985 |
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|Issue 1.1 Copyright (C) J.P.Bowen 1985|
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----------------------------------------------------------------
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----------------------------------------------------------------
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|Mnemon.|Op|HINZC|IXED#RBT|Description |Notes |
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|-------+--+-----+--------+-----------------------+------------|
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|ADC s|F9|*-***| XXXX |Add with Carry |A=A+s+C |
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|ADD s|FB|*-***| XXXX |Add |A=A+s |
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|AND s|F4|--**-| XXXX |Logical AND |A=A&s |
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|ASL d|78|--***| X X |Arithmetic Shift Left |d=d*2 |
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|ASLA |48|--***|X |Arithmetic Shift Left |A=A*2 |
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|ASLX |58|--***|X |Arithmetic Shift Left |X=X*2 |
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|ASR d|77|--***| X X |Arithmetic Shift Right |d=d/2 |
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|ASRA |47|--***|X |Arithmetic Shift Right |A=A/2 |
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|ASRX |57|--***|X |Arithmetic Shift Right |X=X/2 |
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|BCC a|24|-----|X |Branch if Carry Clear |If C=0 |
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|BCLR b|11|-----| X |Bit Clear |b=0 |
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|BCS a|25|-----| X |Branch if Carry Set |If C=1 |
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|BEQ a|27|-----| X |Branch if Equal |If Z=1 |
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|BHCC a|28|-----| X |Branch if Half C. Clear|If H=0 |
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|BHCS a|29|-----| X |Branch if Half C. Set |If H=1 |
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|BHI a|22|-----| X |Branch if Higher |If CvZ=0 |
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|BHS a|24|-----| X |Branch if Higher/Same |If C=0 |
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|BIH a|2F|-----| X |Branch if Int. High |If I=1 |
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|BIL a|2E|-----| X |Branch if Int. Low |If I=0 |
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|BIT s|F5|--**-| XXXX |Bit Test |A&s |
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|BLO a|25|-----| X |Branch if Lower |If C=1 |
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|BLS a|23|-----| X |Branch if Lower or Same|If CvZ=1 |
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|BMC a|2C|-----| X |Branch if Mask Clear |If I=0 |
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|BMI a|2B|-----| X |Branch if Minus |If N=1 |
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|BMS a|2D|-----| X |Branch if Mask Set |If I=1 |
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|BNE a|26|-----| X |Branch if Not Equal |If Z=0 |
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|BPL a|2A|-----| X |Branch if Plus |If N=0 |
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|BRA a|20|-----| X |Branch Always |PC=a |
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|BRN a|21|-----| X |Branch Never |No operation|
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|BRCLR c|01|-----| X|Test for Bit Clear |If b=0 |
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|BRSET c|00|-----| X|Test for Bit Set |If b=1 |
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|BSET b|10|-----| X |Bit Set |b=1 |
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|BSR a|AD|-----|X |Branch to Subroutine |-[SP]=PC,BRA|
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|CLC |98|----0|X |Clear Carry |C=0 |
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|CLI |9A|-0---|X |Clear Interrupt Mask |I=0 |
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|CLR d|7F|--010| X X |Clear |d=0 |
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|CLRA |4F|--010|X |Clear Accumulator |A=0 |
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|CLRX |5F|--010|X |Clear Index register |X=0 |
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|CMP s|F1|--***| XXXX |Compare |A-s |
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|COM d|73|--**1| X X |Complement |d=~d |
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|COMA |43|--**1|X |Complement Accumulator |A=~A |
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|COMX |43|--**1|X |Complement Index reg. |X=~X |
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|CPX s|F3|--***|X |Compare Index register |X-s |
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|DEC d|7A|--**-| X X |Decrement |d=d-1 |
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|DECA |4A|--**-|X |Decrement Accumulator |A=A-1 |
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|DECX |5A|--**-|X |Decrement Index reg. |X=X-1 |
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|EOR s|F8|--**-| XXXX |Logical Exclusive OR |A=Axs |
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|INC d|7C|--**-| X X |Increment |d=d+1 |
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|INCA |4C|--**-|X |Increment Accumulator |A=A+1 |
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|INCX |5C|--**-|X |Increment Index reg. |X=X+1 |
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|JMP d|FC|-----| XXX |Jump |PC=d |
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|JSR d|FD|-----| XXX |Jump to Subroutine |-[SP]=PC,JMP|
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|LDA s|F6|--**-| XXXX |Load Accumulator |A=s |
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|LDX s|FE|--**-| XXXX |Load Index register |X=s |
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|LSL d|78|--0**| X X |Logical Shift Left |d={C,d,0}<- |
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|LSLA |48|--0**|X |Logical Shift Left |A={C,A,0}<- |
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|LSLX |58|--0**|X |Logical Shift Left |X={C,X,0}<- |
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|LSR d|74|--0**| X X |Logical Shift Right |d=->{C,d,0} |
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|LSRA |44|--0**|X |Logical Shift Right |A=->{C,A,0} |
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|LSRX |54|--0**|X |Logical Shift Right |X=->{C,X,0} |
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|NEG d|70|?-***| X X |Negate |d=-d |
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|NEGA |40|?-***|X |Negate Accumulator |A=-A |
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|NEGX |50|?-***|X |Negate Index register |X=-X |
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|NOP |9D|-----|X |No Operation | |
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|ORA s|FA|--**-| XXXX |Logical inclusive OR |A=Avs |
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|ROL d|79|--***| X X |Rotate Left |d={C,d}<- |
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|ROLA |49|--***|X |Rotate Left Accumulator|A={C,A}<- |
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|ROLX |59|--***|X |Rotate Left Index reg. |X={C,X}<- |
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|ROR d|76|--***| X X |Rotate Right |d=->{C,d} |
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|RORA |46|--***|X |Rotate Right Acc. |A=->{C,A} |
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|RORX |56|--***|X |Rotate Right Index reg.|X=->{C,X} |
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|RSP |9C|-----|X |Reset Stack Pointer |SP=007EH |
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|RTI |80|?????|X |Return from Interrupt |{regs}=[SP]+|
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|RTS |81|-----|X |Return from Subroutine |PC=[SP]+ |
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|SBC s|F2|--***| XXXX |Subtract with Carry |A=A-s-C |
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|SEC |99|----0|X |Set Carry |C=1 |
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----------------------------------------------------------------
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----------------------------------------------------------------
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|Mnemon.|Op|HINZC|I#DEXRBT|Description |Notes |
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|-------+--+-----+--------+-----------------------+------------|
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|SEI |9B|-0---|X |Set Interrupt Mask |I=1 |
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|STA d|F7|--**-| XXX |Store Accumulator |d=A |
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|STX d|FF|--**-| XXX |Store Index register |d=X |
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|SUB s|F0|--***| XXXX |Subtract |A=A-s |
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|SWI |83|-----|X |Software Interrupt | |
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|TAX |97|-----|X |Transfer Acc. to Index |X=A |
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|TST s|7D|--**-| X X |Test zero or minus |s |
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|TSTA |4D|--**-|X |Test Accumulator |A |
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|TSTX |5D|--**-|X |Test Index register |X |
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|TXA |9F|-----|X |Transfer Index to Acc. |A=X |
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|----------+-----+--------+------------------------------------|
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| CC |-*01?| |Unaffect/affected/reset/set/unknown |
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| H |H | |Half carry (Bit 4) |
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| I | I | |IRQ interrupt mask (Bit 3) |
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| N | N | |Negative (Bit 2) |
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| Z | Z | |Zero (Bit 1) |
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| C | C| |Carry/borrow (Bit 0) |
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|----------------+--------+------------------------------------|
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| |I |Inherent |
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| X | X |Index (no offset, Op=X) |
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| n,X | X |Index (8-bit offset, Op=X-10H) |
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| nn,X | X |Index (16-bit offset, Op=X-20H) |
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| nn,E | E |Extended (Op=X-30H) |
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| nn | E | ditto when EXTEND is default |
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| n,D | D |Direct (Op=X-40H) |
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| n | D | ditto when DIRECT is default |
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| #n | # |Immediate (Op=X-50H) |
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| a | R |Relative (PC=PC+2+offset) |
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| b | B |Bit set/clear |
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| c | T|Bit test and branch |
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|-------------------------+------------------------------------|
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|DIRECT |Direct addressing mode |
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|EXTEND |Extended addressing mode |
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|FCB n |Form Constant Byte |
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|FCC 'string' |Form Constant Characters |
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|FDB nn |Form Double Byte |
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|RMB nn |Reserve Memory Bytes |
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|-------------------------+------------------------------------|
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| A |Accumulator (8-bit) |
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| CC |Condition Code register (8-bit) |
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| PC |Program Counter (11-bit) |
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| SP |Stack Pointer (11-bit, 61H to 7FH) |
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| X |Index register (8-bit) |
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|-------------------------+------------------------------------|
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| a |Relative address (-125 to +129) |
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| b |Bit (0 to 7), byte (0 to 255) |
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| c |Bit, byte, relative address |
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| d |Destination |
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| n |8-bit expression (0 to 255) |
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| nn |16-bit expression (0 to 65535) |
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| r |Register A or X |
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| s |Source |
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| string |String of ASCII characters |
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|-------------------------+------------------------------------|
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| + |Arithmetic addition |
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| - |Arithmetic subtraction |
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| * |Arithmetic multiplication |
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| / |Arithmetic division |
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| & |Logical AND |
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| ~ |Logical NOT |
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| v |Logical inclusive OR |
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| x |Logical exclusive OR |
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| <- |Rotate left |
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| -> |Rotate right |
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| [ ] |Indirect addressing |
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| [ ]+ |Indirect addressing, auto-increment |
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| -[ ] |Auto-decrement, indirect addressing |
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| { } |Combination of operands |
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| {regs} |All registers {PC,X,A,CC} |
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| $ |Program Counter content |
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|-------------------------+------------------------------------|
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| 0061H to 007FH |Reserved for stack (see RSP) |
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| FFF8H to FFF9H |Hardware interrupt vector |
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| FFFAH to FFFBH |SWI instruction interrupt vector |
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| FFFCH to FFFDH |Non-maskable interrupt vector |
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| FFFEH to FFFFH |Reset vector |
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