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vhd2vl: fix compatibility with verilog 11.0

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This commit is contained in:
Pavol Rusnak 2020-11-14 19:53:42 +01:00
parent 960b4816a5
commit 610d337764
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GPG Key ID: 91F3B339B9A02A3D
1 changed files with 10 additions and 0 deletions
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10
pkgs/applications/science/electronics/vhd2vl/default.nix
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@ -1,5 +1,6 @@
{ stdenv { stdenv
, fetchFromGitHub , fetchFromGitHub
, fetchpatch
, bison , bison
, flex , flex
, verilog , verilog
@ -16,6 +17,15 @@ stdenv.mkDerivation rec {
sha256 = "17va2pil4938j8c93anhy45zzgnvq3k71a7glj02synfrsv6fs8n"; sha256 = "17va2pil4938j8c93anhy45zzgnvq3k71a7glj02synfrsv6fs8n";
}; };
patches = stdenv.lib.optionals (!stdenv.isAarch64) [
# fix build with verilog 11.0 - https://github.com/ldoolitt/vhd2vl/pull/15
# for some strange reason, this is not needed for aarch64
(fetchpatch {
url = "https://github.com/ldoolitt/vhd2vl/commit/ce9b8343ffd004dfe8779a309f4b5a594dbec45e.patch";
sha256 = "1qaqhm2mk66spb2dir9n91b385rarglc067js1g6pcg8mg5v3hhf";
})
];
nativeBuildInputs = [ nativeBuildInputs = [
bison bison
flex flex