1739 lines
82 KiB
Plaintext
1739 lines
82 KiB
Plaintext
6502 Microprocessor
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Most of the following information has been taking out of the "Commodore 64
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Programmers Reference Manual" simply because it was available in electronic
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form and there appears to be no difference between this documentation and
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the 6502 documentation, they are both from the 6500 family after all. I've
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made changes and additions where appropriate.
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In theory you should be able to use any code you can find for emulating
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the 6510 (the C64 processor).
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THE REGISTERS INSIDE THE 6502 MICROPROCESSOR
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Almost all calculations are done in the microprocessor. Registers are
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special pieces of memory in the processor which are used to carry out, and
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store information about calculations. The 6502 has the following registers:
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THE ACCUMULATOR
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This is THE most important register in the microprocessor. Various ma-
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chine language instructions allow you to copy the contents of a memory
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location into the accumulator, copy the contents of the accumulator into
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a memory location, modify the contents of the accumulator or some other
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register directly, without affecting any memory. And the accumulator is
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the only register that has instructions for performing math.
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THE X INDEX REGISTER
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This is a very important register. There are instructions for nearly
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all of the transformations you can make to the accumulator. But there are
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other instructions for things that only the X register can do. Various
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machine language instructions allow you to copy the contents of a memory
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location into the X register, copy the contents of the X register into a
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memory location, and modify the contents of the X, or some other register
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directly.
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THE Y INDEX REGISTER
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This is a very important register. There are instructions for nearly
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all of the transformations you can make to the accumulator, and the X
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register. But there are other instructions for things that only the Y
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register can do. Various machine language instructions allow you to copy
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the contents of a memory location into the Y register, copy the contents
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of the Y register into a memory location, and modify the contents of the
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Y, or some other register directly.
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THE STATUS REGISTER
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This register consists of eight "flags" (a flag = something that indi-
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cates whether something has, or has not occurred). Bits of this register
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are altered depending on the result of arithmetic and logical operations.
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These bits are described below:
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Bit No. 7 6 5 4 3 2 1 0
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S V B D I Z C
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Bit0 - C - Carry flag: this holds the carry out of the most significant
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bit in any arithmetic operation. In subtraction operations however, this
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flag is cleared - set to 0 - if a borrow is required, set to 1 - if no
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borrow is required. The carry flag is also used in shift and rotate
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logical operations.
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Bit1 - Z - Zero flag: this is set to 1 when any arithmetic or logical
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operation produces a zero result, and is set to 0 if the result is
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non-zero.
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Bit 2 - I: this is an interrupt enable/disable flag. If it is set,
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interrupts are disabled. If it is cleared, interrupts are enabled.
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Bit 3 - D: this is the decimal mode status flag. When set, and an Add with
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Carry or Subtract with Carry instruction is executed, the source values are
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treated as valid BCD (Binary Coded Decimal, eg. 0x00-0x99 = 0-99) numbers.
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The result generated is also a BCD number.
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Bit 4 - B: this is set when a software interrupt (BRK instruction) is
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executed.
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Bit 5: not used. Supposed to be logical 1 at all times.
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Bit 6 - V - Overflow flag: when an arithmetic operation produces a result
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too large to be represented in a byte, V is set.
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Bit 7 - S - Sign flag: this is set if the result of an operation is
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negative, cleared if positive.
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The most commonly used flags are C, Z, V, S.
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THE PROGRAM COUNTER
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This contains the address of the current machine language instruction
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being executed. Since the operating system is always "RUN"ning in the
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Commodore VIC-20 (or, for that matter, any computer), the program counter
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is always changing. It could only be stopped by halting the microprocessor
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in some way.
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THE STACK POINTER
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This register contains the location of the first empty place on the
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stack. The stack is used for temporary storage by machine language pro-
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grams, and by the computer.
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ADDRESSING MODES
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Instructions need operands to work on. There are various ways of
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indicating where the processor is to get these operands. The different
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methods used to do this are called addressing modes. The 6502 offers 11
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modes, as described below.
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1) Immediate
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In this mode the operand's value is given in the instruction itself. In
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assembly language this is indicated by "#" before the operand.
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eg. LDA #$0A - means "load the accumulator with the hex value 0A"
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In machine code different modes are indicated by different codes. So LDA
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would be translated into different codes depending on the addressing mode.
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In this mode, it is: $A9 $0A
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2 & 3) Absolute and Zero-page Absolute
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In these modes the operands address is given.
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eg. LDA $31F6 - (assembler)
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$AD $31F6 - (machine code)
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If the address is on zero page - i.e. any address where the high byte is
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00 - only 1 byte is needed for the address. The processor automatically
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fills the 00 high byte.
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eg. LDA $F4
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$A5 $F4
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Note the different instruction codes for the different modes.
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Note also that for 2 byte addresses, the low byte is store first, eg.
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LDA $31F6 is stored as three bytes in memory, $AD $F6 $31.
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Zero-page absolute is usually just called zero-page.
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4) Implied
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No operand addresses are required for this mode. They are implied by the
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instruction.
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eg. TAX - (transfer accumulator contents to X-register)
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$AA
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5) Accumulator
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In this mode the instruction operates on data in the accumulator, so no
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operands are needed.
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eg. LSR - logical bit shift right
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$4A
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6 & 7) Indexed and Zero-page Indexed
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In these modes the address given is added to the value in either the X or
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Y index register to give the actual address of the operand.
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eg. LDA $31F6, Y
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$D9 $31F6
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LDA $31F6, X
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$DD $31F6
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Note that the different operation codes determine the index register used.
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In the zero-page version, you should note that the X and Y registers are
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not interchangeable. Most instructions which can be used with zero-page
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indexing do so with X only.
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eg. LDA $20, X
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$B5 $20
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8) Indirect
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This mode applies only to the JMP instruction - JuMP to new location. It is
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indicated by parenthesis around the operand. The operand is the address of
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the bytes whose value is the new location.
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eg. JMP ($215F)
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Assume the following - byte value
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$215F $76
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$2160 $30
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This instruction takes the value of bytes $215F, $2160 and uses that as the
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address to jump to - i.e. $3076 (remember that addresses are stored with
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low byte first).
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9) Pre-indexed indirect
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In this mode a zer0-page address is added to the contents of the X-register
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to give the address of the bytes holding the address of the operand. The
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indirection is indicated by parenthesis in assembly language.
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eg. LDA ($3E, X)
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$A1 $3E
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Assume the following - byte value
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X-reg. $05
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$0043 $15
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$0044 $24
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$2415 $6E
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Then the instruction is executed by:
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(i) adding $3E and $05 = $0043
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(ii) getting address contained in bytes $0043, $0044 = $2415
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(iii) loading contents of $2415 - i.e. $6E - into accumulator
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Note a) When adding the 1-byte address and the X-register, wrap around
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addition is used - i.e. the sum is always a zero-page address.
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eg. FF + 2 = 0001 not 0101 as you might expect.
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DON'T FORGET THIS WHEN EMULATING THIS MODE.
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b) Only the X register is used in this mode.
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10) Post-indexed indirect
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In this mode the contents of a zero-page address (and the following byte)
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give the indirect addressm which is added to the contents of the Y-register
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to yield the actual address of the operand. Again, inassembly language,
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the instruction is indicated by parenthesis.
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eg. LDA ($4C), Y
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Note that the parenthesis are only around the 2nd byte of the instruction
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since it is the part that does the indirection.
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Assume the following - byte value
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$004C $00
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$004D $21
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Y-reg. $05
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$2105 $6D
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Then the instruction above executes by:
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(i) getting the address in bytes $4C, $4D = $2100
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(ii) adding the contents of the Y-register = $2105
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(111) loading the contents of the byte $2105 - i.e. $6D into the
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accumulator.
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Note: only the Y-register is used in this mode.
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11) Relative
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This mode is used with Branch-on-Condition instructions. It is probably
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the mode you will use most often. A 1 byte value is added to the program
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counter, and the program continues execution from that address. The 1
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byte number is treated as a signed number - i.e. if bit 7 is 1, the number
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given byt bits 0-6 is negative; if bit 7 is 0, the number is positive. This
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enables a branch displacement of up to 127 bytes in either direction.
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eg bit no. 7 6 5 4 3 2 1 0 signed value unsigned value
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value 1 0 1 0 0 1 1 1 -39 $A7
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value 0 0 1 0 0 1 1 1 +39 $27
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Instruction example:
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BEQ $A7
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$F0 $A7
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This instruction will check the zero status bit. If it is set, 39 decimal
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will be subtracted from the program counter and execution continues from
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that address. If the zero status bit is not set, execution continues from
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the following instruction.
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Notes: a) The program counter points to the start of the instruction
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after the branch instruction before the branch displacement is added.
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Remember to take this into account when calculating displacements.
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b) Branch-on-condition instructions work by checking the relevant
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status bits in the status register. Make sure that they have been set or
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unset as you want them. This is often done using a CMP instruction.
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c) If you find you need to branch further than 127 bytes, use the
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opposite branch-on-condition and a JMP.
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+------------------------------------------------------------------------
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| MCS6502 MICROPROCESSOR INSTRUCTION SET - ALPHABETIC SEQUENCE
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+------------------------------------------------------------------------
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| ADC Add Memory to Accumulator with Carry
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| AND "AND" Memory with Accumulator
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| ASL Shift Left One Bit (Memory or Accumulator)
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| BCC Branch on Carry Clear
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| BCS Branch on Carry Set
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| BEQ Branch on Result Zero
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| BIT Test Bits in Memory with Accumulator
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| BMI Branch on Result Minus
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| BNE Branch on Result not Zero
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| BPL Branch on Result Plus
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| BRK Force Break
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| BVC Branch on Overflow Clear
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| BVS Branch on Overflow Set
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| CLC Clear Carry Flag
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| CLD Clear Decimal Mode
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| CLI Clear interrupt Disable Bit
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| CLV Clear Overflow Flag
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| CMP Compare Memory and Accumulator
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| CPX Compare Memory and Index X
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| CPY Compare Memory and Index Y
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| DEC Decrement Memory by One
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| DEX Decrement Index X by One
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| DEY Decrement Index Y by One
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| EOR "Exclusive-Or" Memory with Accumulator
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| INC Increment Memory by One
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| INX Increment Index X by One
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| INY Increment Index Y by One
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| JMP Jump to New Location
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+------------------------------------------------------------------------
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------------------------------------------------------------------------+
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MCS6502 MICROPROCESSOR INSTRUCTION SET - ALPHABETIC SEQUENCE |
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------------------------------------------------------------------------+
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JSR Jump to New Location Saving Return Address |
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LDA Load Accumulator with Memory |
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LDX Load Index X with Memory |
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LDY Load Index Y with Memory |
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LSR Shift Right One Bit (Memory or Accumulator) |
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NOP No Operation |
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ORA "OR" Memory with Accumulator |
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PHA Push Accumulator on Stack |
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PHP Push Processor Status on Stack |
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PLA Pull Accumulator from Stack |
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PLP Pull Processor Status from Stack |
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ROL Rotate One Bit Left (Memory or Accumulator) |
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ROR Rotate One Bit Right (Memory or Accumulator) |
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RTI Return from Interrupt |
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RTS Return from Subroutine |
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SBC Subtract Memory from Accumulator with Borrow |
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SEC Set Carry Flag |
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SED Set Decimal Mode |
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SEI Set Interrupt Disable Status |
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STA Store Accumulator in Memory |
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STX Store Index X in Memory |
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STY Store Index Y in Memory |
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TAX Transfer Accumulator to Index X |
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TAY Transfer Accumulator to Index Y |
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TSX Transfer Stack Pointer to Index X |
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TXA Transfer Index X to Accumulator |
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TXS Transfer Index X to Stack Pointer |
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TYA Transfer Index Y to Accumulator |
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------------------------------------------------------------------------+
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The following notation applies to this summary:
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A Accumulator EOR Logical Exclusive Or
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X, Y Index Registers fromS Transfer from Stack
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M Memory toS Transfer to Stack
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P Processor Status Register -> Transfer to
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S Stack Pointer <- Transfer from
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/ Change V Logical OR
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_ No Change PC Program Counter
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+ Add PCH Program Counter High
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/\ Logical AND PCL Program Counter Low
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- Subtract OPER OPERAND
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# IMMEDIATE ADDRESSING MODE
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Note: At the top of each table is located in parentheses a reference
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number (Ref: XX) which directs the user to that Section in the
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MCS6500 Microcomputer Family Programming Manual in which the
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instruction is defined and discussed.
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ADC Add memory to accumulator with carry ADC
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Operation: A + M + C -> A, C N Z C I D V
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/ / / _ _ /
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(Ref: 2.2.1)
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+----------------+-----------------------+---------+---------+----------+
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| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
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+----------------+-----------------------+---------+---------+----------+
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| Immediate | ADC #Oper | 69 | 2 | 2 |
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| Zero Page | ADC Oper | 65 | 2 | 3 |
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| Zero Page,X | ADC Oper,X | 75 | 2 | 4 |
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| Absolute | ADC Oper | 60 | 3 | 4 |
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| Absolute,X | ADC Oper,X | 70 | 3 | 4* |
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| Absolute,Y | ADC Oper,Y | 79 | 3 | 4* |
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| (Indirect,X) | ADC (Oper,X) | 61 | 2 | 6 |
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| (Indirect),Y | ADC (Oper),Y | 71 | 2 | 5* |
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+----------------+-----------------------+---------+---------+----------+
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* Add 1 if page boundary is crossed.
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AND "AND" memory with accumulator AND
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Operation: A /\ M -> A N Z C I D V
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/ / _ _ _ _
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(Ref: 2.2.3.0)
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+----------------+-----------------------+---------+---------+----------+
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| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
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+----------------+-----------------------+---------+---------+----------+
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| Immediate | AND #Oper | 29 | 2 | 2 |
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| Zero Page | AND Oper | 25 | 2 | 3 |
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| Zero Page,X | AND Oper,X | 35 | 2 | 4 |
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| Absolute | AND Oper | 2D | 3 | 4 |
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| Absolute,X | AND Oper,X | 3D | 3 | 4* |
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| Absolute,Y | AND Oper,Y | 39 | 3 | 4* |
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| (Indirect,X) | AND (Oper,X) | 21 | 2 | 6 |
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| (Indirect,Y) | AND (Oper),Y | 31 | 2 | 5 |
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+----------------+-----------------------+---------+---------+----------+
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* Add 1 if page boundary is crossed.
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ASL ASL Shift Left One Bit (Memory or Accumulator) ASL
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+-+-+-+-+-+-+-+-+
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Operation: C <- |7|6|5|4|3|2|1|0| <- 0
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+-+-+-+-+-+-+-+-+ N Z C I D V
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/ / / _ _ _
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(Ref: 10.2)
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+----------------+-----------------------+---------+---------+----------+
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| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
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+----------------+-----------------------+---------+---------+----------+
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| Accumulator | ASL A | 0A | 1 | 2 |
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| Zero Page | ASL Oper | 06 | 2 | 5 |
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| Zero Page,X | ASL Oper,X | 16 | 2 | 6 |
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| Absolute | ASL Oper | 0E | 3 | 6 |
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| Absolute, X | ASL Oper,X | 1E | 3 | 7 |
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+----------------+-----------------------+---------+---------+----------+
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BCC BCC Branch on Carry Clear BCC
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N Z C I D V
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Operation: Branch on C = 0 _ _ _ _ _ _
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(Ref: 4.1.1.3)
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+----------------+-----------------------+---------+---------+----------+
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| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
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+----------------+-----------------------+---------+---------+----------+
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| Relative | BCC Oper | 90 | 2 | 2* |
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+----------------+-----------------------+---------+---------+----------+
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* Add 1 if branch occurs to same page.
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* Add 2 if branch occurs to different page.
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BCS BCS Branch on carry set BCS
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Operation: Branch on C = 1 N Z C I D V
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_ _ _ _ _ _
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(Ref: 4.1.1.4)
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+----------------+-----------------------+---------+---------+----------+
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| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
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+----------------+-----------------------+---------+---------+----------+
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| Relative | BCS Oper | B0 | 2 | 2* |
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+----------------+-----------------------+---------+---------+----------+
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* Add 1 if branch occurs to same page.
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* Add 2 if branch occurs to next page.
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BEQ BEQ Branch on result zero BEQ
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N Z C I D V
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Operation: Branch on Z = 1 _ _ _ _ _ _
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(Ref: 4.1.1.5)
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+----------------+-----------------------+---------+---------+----------+
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| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
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+----------------+-----------------------+---------+---------+----------+
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| Relative | BEQ Oper | F0 | 2 | 2* |
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+----------------+-----------------------+---------+---------+----------+
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* Add 1 if branch occurs to same page.
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* Add 2 if branch occurs to next page.
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BIT BIT Test bits in memory with accumulator BIT
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Operation: A /\ M, M7 -> N, M6 -> V
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Bit 6 and 7 are transferred to the status register. N Z C I D V
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If the result of A /\ M is zero then Z = 1, otherwise M7/ _ _ _ M6
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Z = 0
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(Ref: 4.2.1.1)
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+----------------+-----------------------+---------+---------+----------+
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| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
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+----------------+-----------------------+---------+---------+----------+
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| Zero Page | BIT Oper | 24 | 2 | 3 |
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| Absolute | BIT Oper | 2C | 3 | 4 |
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+----------------+-----------------------+---------+---------+----------+
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BMI BMI Branch on result minus BMI
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Operation: Branch on N = 1 N Z C I D V
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_ _ _ _ _ _
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(Ref: 4.1.1.1)
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+----------------+-----------------------+---------+---------+----------+
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| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
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+----------------+-----------------------+---------+---------+----------+
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| Relative | BMI Oper | 30 | 2 | 2* |
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+----------------+-----------------------+---------+---------+----------+
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* Add 1 if branch occurs to same page.
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* Add 1 if branch occurs to different page.
|
|
|
|
|
|
BNE BNE Branch on result not zero BNE
|
|
|
|
Operation: Branch on Z = 0 N Z C I D V
|
|
_ _ _ _ _ _
|
|
(Ref: 4.1.1.6)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Relative | BMI Oper | D0 | 2 | 2* |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
* Add 1 if branch occurs to same page.
|
|
* Add 2 if branch occurs to different page.
|
|
|
|
|
|
BPL BPL Branch on result plus BPL
|
|
|
|
Operation: Branch on N = 0 N Z C I D V
|
|
_ _ _ _ _ _
|
|
(Ref: 4.1.1.2)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Relative | BPL Oper | 10 | 2 | 2* |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
* Add 1 if branch occurs to same page.
|
|
* Add 2 if branch occurs to different page.
|
|
|
|
|
|
BRK BRK Force Break BRK
|
|
|
|
Operation: Forced Interrupt PC + 2 toS P toS N Z C I D V
|
|
_ _ _ 1 _ _
|
|
(Ref: 9.11)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Implied | BRK | 00 | 1 | 7 |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
1. A BRK command cannot be masked by setting I.
|
|
|
|
|
|
BVC BVC Branch on overflow clear BVC
|
|
|
|
Operation: Branch on V = 0 N Z C I D V
|
|
_ _ _ _ _ _
|
|
(Ref: 4.1.1.8)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Relative | BVC Oper | 50 | 2 | 2* |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
* Add 1 if branch occurs to same page.
|
|
* Add 2 if branch occurs to different page.
|
|
|
|
|
|
BVS BVS Branch on overflow set BVS
|
|
|
|
Operation: Branch on V = 1 N Z C I D V
|
|
_ _ _ _ _ _
|
|
(Ref: 4.1.1.7)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Relative | BVS Oper | 70 | 2 | 2* |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
* Add 1 if branch occurs to same page.
|
|
* Add 2 if branch occurs to different page.
|
|
|
|
|
|
CLC CLC Clear carry flag CLC
|
|
|
|
Operation: 0 -> C N Z C I D V
|
|
_ _ 0 _ _ _
|
|
(Ref: 3.0.2)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Implied | CLC | 18 | 1 | 2 |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
|
|
|
|
CLD CLD Clear decimal mode CLD
|
|
|
|
Operation: 0 -> D N A C I D V
|
|
_ _ _ _ 0 _
|
|
(Ref: 3.3.2)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Implied | CLD | D8 | 1 | 2 |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
|
|
|
|
CLI CLI Clear interrupt disable bit CLI
|
|
|
|
Operation: 0 -> I N Z C I D V
|
|
_ _ _ 0 _ _
|
|
(Ref: 3.2.2)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Implied | CLI | 58 | 1 | 2 |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
|
|
|
|
CLV CLV Clear overflow flag CLV
|
|
|
|
Operation: 0 -> V N Z C I D V
|
|
_ _ _ _ _ 0
|
|
(Ref: 3.6.1)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Implied | CLV | B8 | 1 | 2 |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
|
|
|
|
CMP CMP Compare memory and accumulator CMP
|
|
|
|
Operation: A - M N Z C I D V
|
|
/ / / _ _ _
|
|
(Ref: 4.2.1)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Immediate | CMP #Oper | C9 | 2 | 2 |
|
|
| Zero Page | CMP Oper | C5 | 2 | 3 |
|
|
| Zero Page,X | CMP Oper,X | D5 | 2 | 4 |
|
|
| Absolute | CMP Oper | CD | 3 | 4 |
|
|
| Absolute,X | CMP Oper,X | DD | 3 | 4* |
|
|
| Absolute,Y | CMP Oper,Y | D9 | 3 | 4* |
|
|
| (Indirect,X) | CMP (Oper,X) | C1 | 2 | 6 |
|
|
| (Indirect),Y | CMP (Oper),Y | D1 | 2 | 5* |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
* Add 1 if page boundary is crossed.
|
|
|
|
CPX CPX Compare Memory and Index X CPX
|
|
N Z C I D V
|
|
Operation: X - M / / / _ _ _
|
|
(Ref: 7.8)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Immediate | CPX *Oper | E0 | 2 | 2 |
|
|
| Zero Page | CPX Oper | E4 | 2 | 3 |
|
|
| Absolute | CPX Oper | EC | 3 | 4 |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
|
|
CPY CPY Compare memory and index Y CPY
|
|
N Z C I D V
|
|
Operation: Y - M / / / _ _ _
|
|
(Ref: 7.9)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Immediate | CPY *Oper | C0 | 2 | 2 |
|
|
| Zero Page | CPY Oper | C4 | 2 | 3 |
|
|
| Absolute | CPY Oper | CC | 3 | 4 |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
|
|
|
|
DEC DEC Decrement memory by one DEC
|
|
|
|
Operation: M - 1 -> M N Z C I D V
|
|
/ / _ _ _ _
|
|
(Ref: 10.7)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Zero Page | DEC Oper | C6 | 2 | 5 |
|
|
| Zero Page,X | DEC Oper,X | D6 | 2 | 6 |
|
|
| Absolute | DEC Oper | CE | 3 | 6 |
|
|
| Absolute,X | DEC Oper,X | DE | 3 | 7 |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
|
|
|
|
DEX DEX Decrement index X by one DEX
|
|
|
|
Operation: X - 1 -> X N Z C I D V
|
|
/ / _ _ _ _
|
|
(Ref: 7.6)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Implied | DEX | CA | 1 | 2 |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
|
|
|
|
DEY DEY Decrement index Y by one DEY
|
|
|
|
Operation: X - 1 -> Y N Z C I D V
|
|
/ / _ _ _ _
|
|
(Ref: 7.7)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Implied | DEY | 88 | 1 | 2 |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
|
|
|
|
EOR EOR "Exclusive-Or" memory with accumulator EOR
|
|
|
|
Operation: A EOR M -> A N Z C I D V
|
|
/ / _ _ _ _
|
|
(Ref: 2.2.3.2)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Immediate | EOR #Oper | 49 | 2 | 2 |
|
|
| Zero Page | EOR Oper | 45 | 2 | 3 |
|
|
| Zero Page,X | EOR Oper,X | 55 | 2 | 4 |
|
|
| Absolute | EOR Oper | 40 | 3 | 4 |
|
|
| Absolute,X | EOR Oper,X | 50 | 3 | 4* |
|
|
| Absolute,Y | EOR Oper,Y | 59 | 3 | 4* |
|
|
| (Indirect,X) | EOR (Oper,X) | 41 | 2 | 6 |
|
|
| (Indirect),Y | EOR (Oper),Y | 51 | 2 | 5* |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
* Add 1 if page boundary is crossed.
|
|
|
|
INC INC Increment memory by one INC
|
|
N Z C I D V
|
|
Operation: M + 1 -> M / / _ _ _ _
|
|
(Ref: 10.6)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Zero Page | INC Oper | E6 | 2 | 5 |
|
|
| Zero Page,X | INC Oper,X | F6 | 2 | 6 |
|
|
| Absolute | INC Oper | EE | 3 | 6 |
|
|
| Absolute,X | INC Oper,X | FE | 3 | 7 |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
|
|
INX INX Increment Index X by one INX
|
|
N Z C I D V
|
|
Operation: X + 1 -> X / / _ _ _ _
|
|
(Ref: 7.4)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Implied | INX | E8 | 1 | 2 |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
|
|
|
|
INY INY Increment Index Y by one INY
|
|
|
|
Operation: X + 1 -> X N Z C I D V
|
|
/ / _ _ _ _
|
|
(Ref: 7.5)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Implied | INY | C8 | 1 | 2 |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
|
|
|
|
JMP JMP Jump to new location JMP
|
|
|
|
Operation: (PC + 1) -> PCL N Z C I D V
|
|
(PC + 2) -> PCH (Ref: 4.0.2) _ _ _ _ _ _
|
|
(Ref: 9.8.1)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Absolute | JMP Oper | 4C | 3 | 3 |
|
|
| Indirect | JMP (Oper) | 6C | 3 | 5 |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
|
|
|
|
JSR JSR Jump to new location saving return address JSR
|
|
|
|
Operation: PC + 2 toS, (PC + 1) -> PCL N Z C I D V
|
|
(PC + 2) -> PCH _ _ _ _ _ _
|
|
(Ref: 8.1)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Absolute | JSR Oper | 20 | 3 | 6 |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
|
|
|
|
LDA LDA Load accumulator with memory LDA
|
|
|
|
Operation: M -> A N Z C I D V
|
|
/ / _ _ _ _
|
|
(Ref: 2.1.1)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Immediate | LDA #Oper | A9 | 2 | 2 |
|
|
| Zero Page | LDA Oper | A5 | 2 | 3 |
|
|
| Zero Page,X | LDA Oper,X | B5 | 2 | 4 |
|
|
| Absolute | LDA Oper | AD | 3 | 4 |
|
|
| Absolute,X | LDA Oper,X | BD | 3 | 4* |
|
|
| Absolute,Y | LDA Oper,Y | B9 | 3 | 4* |
|
|
| (Indirect,X) | LDA (Oper,X) | A1 | 2 | 6 |
|
|
| (Indirect),Y | LDA (Oper),Y | B1 | 2 | 5* |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
* Add 1 if page boundary is crossed.
|
|
|
|
|
|
LDX LDX Load index X with memory LDX
|
|
|
|
Operation: M -> X N Z C I D V
|
|
/ / _ _ _ _
|
|
(Ref: 7.0)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Immediate | LDX #Oper | A2 | 2 | 2 |
|
|
| Zero Page | LDX Oper | A6 | 2 | 3 |
|
|
| Zero Page,Y | LDX Oper,Y | B6 | 2 | 4 |
|
|
| Absolute | LDX Oper | AE | 3 | 4 |
|
|
| Absolute,Y | LDX Oper,Y | BE | 3 | 4* |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
* Add 1 when page boundary is crossed.
|
|
|
|
|
|
LDY LDY Load index Y with memory LDY
|
|
N Z C I D V
|
|
Operation: M -> Y / / _ _ _ _
|
|
(Ref: 7.1)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Immediate | LDY #Oper | A0 | 2 | 2 |
|
|
| Zero Page | LDY Oper | A4 | 2 | 3 |
|
|
| Zero Page,X | LDY Oper,X | B4 | 2 | 4 |
|
|
| Absolute | LDY Oper | AC | 3 | 4 |
|
|
| Absolute,X | LDY Oper,X | BC | 3 | 4* |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
* Add 1 when page boundary is crossed.
|
|
|
|
|
|
LSR LSR Shift right one bit (memory or accumulator) LSR
|
|
|
|
+-+-+-+-+-+-+-+-+
|
|
Operation: 0 -> |7|6|5|4|3|2|1|0| -> C N Z C I D V
|
|
+-+-+-+-+-+-+-+-+ 0 / / _ _ _
|
|
(Ref: 10.1)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Accumulator | LSR A | 4A | 1 | 2 |
|
|
| Zero Page | LSR Oper | 46 | 2 | 5 |
|
|
| Zero Page,X | LSR Oper,X | 56 | 2 | 6 |
|
|
| Absolute | LSR Oper | 4E | 3 | 6 |
|
|
| Absolute,X | LSR Oper,X | 5E | 3 | 7 |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
|
|
|
|
NOP NOP No operation NOP
|
|
N Z C I D V
|
|
Operation: No Operation (2 cycles) _ _ _ _ _ _
|
|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Implied | NOP | EA | 1 | 2 |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
|
|
|
|
ORA ORA "OR" memory with accumulator ORA
|
|
|
|
Operation: A V M -> A N Z C I D V
|
|
/ / _ _ _ _
|
|
(Ref: 2.2.3.1)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Immediate | ORA #Oper | 09 | 2 | 2 |
|
|
| Zero Page | ORA Oper | 05 | 2 | 3 |
|
|
| Zero Page,X | ORA Oper,X | 15 | 2 | 4 |
|
|
| Absolute | ORA Oper | 0D | 3 | 4 |
|
|
| Absolute,X | ORA Oper,X | 10 | 3 | 4* |
|
|
| Absolute,Y | ORA Oper,Y | 19 | 3 | 4* |
|
|
| (Indirect,X) | ORA (Oper,X) | 01 | 2 | 6 |
|
|
| (Indirect),Y | ORA (Oper),Y | 11 | 2 | 5 |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
* Add 1 on page crossing
|
|
|
|
|
|
PHA PHA Push accumulator on stack PHA
|
|
|
|
Operation: A toS N Z C I D V
|
|
_ _ _ _ _ _
|
|
(Ref: 8.5)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Implied | PHA | 48 | 1 | 3 |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
|
|
|
|
PHP PHP Push processor status on stack PHP
|
|
|
|
Operation: P toS N Z C I D V
|
|
_ _ _ _ _ _
|
|
(Ref: 8.11)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Implied | PHP | 08 | 1 | 3 |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
|
|
|
|
PLA PLA Pull accumulator from stack PLA
|
|
|
|
Operation: A fromS N Z C I D V
|
|
_ _ _ _ _ _
|
|
(Ref: 8.6)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Implied | PLA | 68 | 1 | 4 |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
|
|
|
|
PLP PLP Pull processor status from stack PLA
|
|
|
|
Operation: P fromS N Z C I D V
|
|
From Stack
|
|
(Ref: 8.12)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Implied | PLP | 28 | 1 | 4 |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
|
|
|
|
ROL ROL Rotate one bit left (memory or accumulator) ROL
|
|
|
|
+------------------------------+
|
|
| M or A |
|
|
| +-+-+-+-+-+-+-+-+ +-+ |
|
|
Operation: +-< |7|6|5|4|3|2|1|0| <- |C| <-+ N Z C I D V
|
|
+-+-+-+-+-+-+-+-+ +-+ / / / _ _ _
|
|
(Ref: 10.3)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Accumulator | ROL A | 2A | 1 | 2 |
|
|
| Zero Page | ROL Oper | 26 | 2 | 5 |
|
|
| Zero Page,X | ROL Oper,X | 36 | 2 | 6 |
|
|
| Absolute | ROL Oper | 2E | 3 | 6 |
|
|
| Absolute,X | ROL Oper,X | 3E | 3 | 7 |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
|
|
|
|
ROR ROR Rotate one bit right (memory or accumulator) ROR
|
|
|
|
+------------------------------+
|
|
| |
|
|
| +-+ +-+-+-+-+-+-+-+-+ |
|
|
Operation: +-> |C| -> |7|6|5|4|3|2|1|0| >-+ N Z C I D V
|
|
+-+ +-+-+-+-+-+-+-+-+ / / / _ _ _
|
|
(Ref: 10.4)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Accumulator | ROR A | 6A | 1 | 2 |
|
|
| Zero Page | ROR Oper | 66 | 2 | 5 |
|
|
| Zero Page,X | ROR Oper,X | 76 | 2 | 6 |
|
|
| Absolute | ROR Oper | 6E | 3 | 6 |
|
|
| Absolute,X | ROR Oper,X | 7E | 3 | 7 |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
|
|
Note: ROR instruction is available on MCS650X microprocessors after
|
|
June, 1976.
|
|
|
|
|
|
RTI RTI Return from interrupt RTI
|
|
N Z C I D V
|
|
Operation: P fromS PC fromS From Stack
|
|
(Ref: 9.6)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Implied | RTI | 4D | 1 | 6 |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
|
|
|
|
RTS RTS Return from subroutine RTS
|
|
N Z C I D V
|
|
Operation: PC fromS, PC + 1 -> PC _ _ _ _ _ _
|
|
(Ref: 8.2)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Implied | RTS | 60 | 1 | 6 |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
|
|
|
|
SBC SBC Subtract memory from accumulator with borrow SBC
|
|
-
|
|
Operation: A - M - C -> A N Z C I D V
|
|
- / / / _ _ /
|
|
Note:C = Borrow (Ref: 2.2.2)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Immediate | SBC #Oper | E9 | 2 | 2 |
|
|
| Zero Page | SBC Oper | E5 | 2 | 3 |
|
|
| Zero Page,X | SBC Oper,X | F5 | 2 | 4 |
|
|
| Absolute | SBC Oper | ED | 3 | 4 |
|
|
| Absolute,X | SBC Oper,X | FD | 3 | 4* |
|
|
| Absolute,Y | SBC Oper,Y | F9 | 3 | 4* |
|
|
| (Indirect,X) | SBC (Oper,X) | E1 | 2 | 6 |
|
|
| (Indirect),Y | SBC (Oper),Y | F1 | 2 | 5 |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
* Add 1 when page boundary is crossed.
|
|
|
|
|
|
SEC SEC Set carry flag SEC
|
|
|
|
Operation: 1 -> C N Z C I D V
|
|
_ _ 1 _ _ _
|
|
(Ref: 3.0.1)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Implied | SEC | 38 | 1 | 2 |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
|
|
|
|
SED SED Set decimal mode SED
|
|
N Z C I D V
|
|
Operation: 1 -> D _ _ _ _ 1 _
|
|
(Ref: 3.3.1)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Implied | SED | F8 | 1 | 2 |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
|
|
|
|
SEI SEI Set interrupt disable status SED
|
|
N Z C I D V
|
|
Operation: 1 -> I _ _ _ 1 _ _
|
|
(Ref: 3.2.1)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Implied | SEI | 78 | 1 | 2 |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
|
|
|
|
STA STA Store accumulator in memory STA
|
|
|
|
Operation: A -> M N Z C I D V
|
|
_ _ _ _ _ _
|
|
(Ref: 2.1.2)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Zero Page | STA Oper | 85 | 2 | 3 |
|
|
| Zero Page,X | STA Oper,X | 95 | 2 | 4 |
|
|
| Absolute | STA Oper | 80 | 3 | 4 |
|
|
| Absolute,X | STA Oper,X | 90 | 3 | 5 |
|
|
| Absolute,Y | STA Oper, Y | 99 | 3 | 5 |
|
|
| (Indirect,X) | STA (Oper,X) | 81 | 2 | 6 |
|
|
| (Indirect),Y | STA (Oper),Y | 91 | 2 | 6 |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
|
|
|
|
STX STX Store index X in memory STX
|
|
|
|
Operation: X -> M N Z C I D V
|
|
_ _ _ _ _ _
|
|
(Ref: 7.2)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Zero Page | STX Oper | 86 | 2 | 3 |
|
|
| Zero Page,Y | STX Oper,Y | 96 | 2 | 4 |
|
|
| Absolute | STX Oper | 8E | 3 | 4 |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
|
|
|
|
STY STY Store index Y in memory STY
|
|
|
|
Operation: Y -> M N Z C I D V
|
|
_ _ _ _ _ _
|
|
(Ref: 7.3)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Zero Page | STY Oper | 84 | 2 | 3 |
|
|
| Zero Page,X | STY Oper,X | 94 | 2 | 4 |
|
|
| Absolute | STY Oper | 8C | 3 | 4 |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
|
|
|
|
TAX TAX Transfer accumulator to index X TAX
|
|
|
|
Operation: A -> X N Z C I D V
|
|
/ / _ _ _ _
|
|
(Ref: 7.11)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Implied | TAX | AA | 1 | 2 |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
|
|
|
|
TAY TAY Transfer accumulator to index Y TAY
|
|
|
|
Operation: A -> Y N Z C I D V
|
|
/ / _ _ _ _
|
|
(Ref: 7.13)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Implied | TAY | A8 | 1 | 2 |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
|
|
|
|
TSX TSX Transfer stack pointer to index X TSX
|
|
|
|
Operation: S -> X N Z C I D V
|
|
/ / _ _ _ _
|
|
(Ref: 8.9)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Implied | TSX | BA | 1 | 2 |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
|
|
TXA TXA Transfer index X to accumulator TXA
|
|
N Z C I D V
|
|
Operation: X -> A / / _ _ _ _
|
|
(Ref: 7.12)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Implied | TXA | 8A | 1 | 2 |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
|
|
TXS TXS Transfer index X to stack pointer TXS
|
|
N Z C I D V
|
|
Operation: X -> S _ _ _ _ _ _
|
|
(Ref: 8.8)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Implied | TXS | 9A | 1 | 2 |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
|
|
TYA TYA Transfer index Y to accumulator TYA
|
|
|
|
Operation: Y -> A N Z C I D V
|
|
/ / _ _ _ _
|
|
(Ref: 7.14)
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Addressing Mode| Assembly Language Form| OP CODE |No. Bytes|No. Cycles|
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
| Implied | TYA | 98 | 1 | 2 |
|
|
+----------------+-----------------------+---------+---------+----------+
|
|
|
|
|
|
|
|
+------------------------------------------------------------------------
|
|
| INSTRUCTION ADDRESSING MODES AND RELATED EXECUTION TIMES
|
|
| (in clock cycles)
|
|
+------------------------------------------------------------------------
|
|
|
|
A A A B B B B B B B B B B C
|
|
D N S C C E I M N P R V V L
|
|
C D L C S Q T I E L K C S C
|
|
Accumulator | . . 2 . . . . . . . . . . .
|
|
Immediate | 2 2 . . . . . . . . . . .
|
|
Zero Page | 3 3 5 . . . 3 . . . . . . .
|
|
Zero Page,X | 4 4 6 . . . . . . . . . . .
|
|
Zero Page,Y | . . . . . . . . . . . . . .
|
|
Absolute | 4 4 6 . . . 4 . . . . . . .
|
|
Absolute,X | 4* 4* 7 . . . . . . . . . . .
|
|
Absolute,Y | 4* 4* . . . . . . . . . . . .
|
|
Implied | . . . . . . . . . . . . . 2
|
|
Relative | . . . 2** 2** 2** . 2** 2** 2** 7 2** 2** .
|
|
(Indirect,X) | 6 6 . . . . . . . . . . . .
|
|
(Indirect),Y | 5* 5* . . . . . . . . . . . .
|
|
Abs. Indirect| . . . . . . . . . . . . . .
|
|
+-----------------------------------------------------------
|
|
C C C C C C D D D E I I I J
|
|
L L L M P P E E E O N N N M
|
|
D I V P X Y C X Y R C X Y P
|
|
Accumulator | . . . . . . . . . . . . . .
|
|
Immediate | . . . 2 2 2 . . . 2 . . . .
|
|
Zero Page | . . . 3 3 3 5 . . 3 5 . . .
|
|
Zero Page,X | . . . 4 . . 6 . . 4 6 . . .
|
|
Zero Page,Y | . . . . . . . . . . . . . .
|
|
Absolute | . . . 4 4 4 6 . . 4 6 . . 3
|
|
Absolute,X | . . . 4* . . 7 . . 4* 7 . . .
|
|
Absolute,Y | . . . 4* . . . . . 4* . . . .
|
|
Implied | 2 2 2 . . . . 2 2 . . 2 2 .
|
|
Relative | . . . . . . . . . . . . . .
|
|
(Indirect,X) | . . . 6 . . . . . 6 . . . .
|
|
(Indirect),Y | . . . 5* . . . . . 5* . . . .
|
|
Abs. Indirect| . . . . . . . . . . . . . 5
|
|
+-----------------------------------------------------------
|
|
* Add one cycle if indexing across page boundary
|
|
** Add one cycle if branch is taken, Add one additional if branching
|
|
operation crosses page boundary
|
|
|
|
|
|
------------------------------------------------------------------------+
|
|
INSTRUCTION ADDRESSING MODES AND RELATED EXECUTION TIMES |
|
|
(in clock cycles) |
|
|
------------------------------------------------------------------------+
|
|
|
|
J L L L L N O P P P P R R R
|
|
S D D D S O R H H L L O O T
|
|
R A X Y R P A A P A P L R I
|
|
Accumulator | . . . . 2 . . . . . . 2 2 .
|
|
Immediate | . 2 2 2 . . 2 . . . . . . .
|
|
Zero Page | . 3 3 3 5 . 3 . . . . 5 5 .
|
|
Zero Page,X | . 4 . 4 6 . 4 . . . . 6 6 .
|
|
Zero Page,Y | . . 4 . . . . . . . . . . .
|
|
Absolute | 6 4 4 4 6 . 4 . . . . 6 6 .
|
|
Absolute,X | . 4* . 4* 7 . 4* . . . . 7 7 .
|
|
Absolute,Y | . 4* 4* . . . 4* . . . . . . .
|
|
Implied | . . . . . 2 . 3 3 4 4 . . 6
|
|
Relative | . . . . . . . . . . . . . .
|
|
(Indirect,X) | . 6 . . . . 6 . . . . . . .
|
|
(Indirect),Y | . 5* . . . . 5* . . . . . . .
|
|
Abs. Indirect| . . . . . . . . . . . . . .
|
|
+-----------------------------------------------------------
|
|
R S S S S S S S T T T T T T
|
|
T B E E E T T T A A S X X Y
|
|
S C C D I A X Y X Y X A S A
|
|
Accumulator | . . . . . . . . . . . . . .
|
|
Immediate | . 2 . . . . . . . . . . . .
|
|
Zero Page | . 3 . . . 3 3 3 . . . . . .
|
|
Zero Page,X | . 4 . . . 4 . 4 . . . . . .
|
|
Zero Page,Y | . . . . . . 4 . . . . . . .
|
|
Absolute | . 4 . . . 4 4 4 . . . . . .
|
|
Absolute,X | . 4* . . . 5 . . . . . . . .
|
|
Absolute,Y | . 4* . . . 5 . . . . . . . .
|
|
Implied | 6 . 2 2 2 . . . 2 2 2 2 2 2
|
|
Relative | . . . . . . . . . . . . . .
|
|
(Indirect,X) | . 6 . . . 6 . . . . . . . .
|
|
(Indirect),Y | . 5* . . . 6 . . . . . . . .
|
|
Abs. Indirect| . . . . . . . . . . . . . .
|
|
+-----------------------------------------------------------
|
|
* Add one cycle if indexing across page boundary
|
|
** Add one cycle if branch is taken, Add one additional if branching
|
|
operation crosses page boundary
|
|
|
|
|
|
|
|
00 - BRK 20 - JSR
|
|
01 - ORA - (Indirect,X) 21 - AND - (Indirect,X)
|
|
02 - Future Expansion 22 - Future Expansion
|
|
03 - Future Expansion 23 - Future Expansion
|
|
04 - Future Expansion 24 - BIT - Zero Page
|
|
05 - ORA - Zero Page 25 - AND - Zero Page
|
|
06 - ASL - Zero Page 26 - ROL - Zero Page
|
|
07 - Future Expansion 27 - Future Expansion
|
|
08 - PHP 28 - PLP
|
|
09 - ORA - Immediate 29 - AND - Immediate
|
|
0A - ASL - Accumulator 2A - ROL - Accumulator
|
|
0B - Future Expansion 2B - Future Expansion
|
|
0C - Future Expansion 2C - BIT - Absolute
|
|
0D - ORA - Absolute 2D - AND - Absolute
|
|
0E - ASL - Absolute 2E - ROL - Absolute
|
|
0F - Future Expansion 2F - Future Expansion
|
|
10 - BPL 30 - BMI
|
|
11 - ORA - (Indirect),Y 31 - AND - (Indirect),Y
|
|
12 - Future Expansion 32 - Future Expansion
|
|
13 - Future Expansion 33 - Future Expansion
|
|
14 - Future Expansion 34 - Future Expansion
|
|
15 - ORA - Zero Page,X 35 - AND - Zero Page,X
|
|
16 - ASL - Zero Page,X 36 - ROL - Zero Page,X
|
|
17 - Future Expansion 37 - Future Expansion
|
|
18 - CLC 38 - SEC
|
|
19 - ORA - Absolute,Y 39 - AND - Absolute,Y
|
|
1A - Future Expansion 3A - Future Expansion
|
|
1B - Future Expansion 3B - Future Expansion
|
|
1C - Future Expansion 3C - Future Expansion
|
|
1D - ORA - Absolute,X 3D - AND - Absolute,X
|
|
1E - ASL - Absolute,X 3E - ROL - Absolute,X
|
|
1F - Future Expansion 3F - Future Expansion
|
|
|
|
40 - RTI 60 - RTS
|
|
41 - EOR - (Indirect,X) 61 - ADC - (Indirect,X)
|
|
42 - Future Expansion 62 - Future Expansion
|
|
43 - Future Expansion 63 - Future Expansion
|
|
44 - Future Expansion 64 - Future Expansion
|
|
45 - EOR - Zero Page 65 - ADC - Zero Page
|
|
46 - LSR - Zero Page 66 - ROR - Zero Page
|
|
47 - Future Expansion 67 - Future Expansion
|
|
48 - PHA 68 - PLA
|
|
49 - EOR - Immediate 69 - ADC - Immediate
|
|
4A - LSR - Accumulator 6A - ROR - Accumulator
|
|
4B - Future Expansion 6B - Future Expansion
|
|
4C - JMP - Absolute 6C - JMP - Indirect
|
|
4D - EOR - Absolute 6D - ADC - Absolute
|
|
4E - LSR - Absolute 6E - ROR - Absolute
|
|
4F - Future Expansion 6F - Future Expansion
|
|
50 - BVC 70 - BVS
|
|
51 - EOR - (Indirect),Y 71 - ADC - (Indirect),Y
|
|
52 - Future Expansion 72 - Future Expansion
|
|
53 - Future Expansion 73 - Future Expansion
|
|
54 - Future Expansion 74 - Future Expansion
|
|
55 - EOR - Zero Page,X 75 - ADC - Zero Page,X
|
|
56 - LSR - Zero Page,X 76 - ROR - Zero Page,X
|
|
57 - Future Expansion 77 - Future Expansion
|
|
58 - CLI 78 - SEI
|
|
59 - EOR - Absolute,Y 79 - ADC - Absolute,Y
|
|
5A - Future Expansion 7A - Future Expansion
|
|
5B - Future Expansion 7B - Future Expansion
|
|
5C - Future Expansion 7C - Future Expansion
|
|
50 - EOR - Absolute,X 70 - ADC - Absolute,X
|
|
5E - LSR - Absolute,X 7E - ROR - Absolute,X
|
|
5F - Future Expansion 7F - Future Expansion
|
|
|
|
80 - Future Expansion A0 - LDY - Immediate
|
|
81 - STA - (Indirect,X) A1 - LDA - (Indirect,X)
|
|
82 - Future Expansion A2 - LDX - Immediate
|
|
83 - Future Expansion A3 - Future Expansion
|
|
84 - STY - Zero Page A4 - LDY - Zero Page
|
|
85 - STA - Zero Page A5 - LDA - Zero Page
|
|
86 - STX - Zero Page A6 - LDX - Zero Page
|
|
87 - Future Expansion A7 - Future Expansion
|
|
88 - DEY A8 - TAY
|
|
89 - Future Expansion A9 - LDA - Immediate
|
|
8A - TXA AA - TAX
|
|
8B - Future Expansion AB - Future Expansion
|
|
8C - STY - Absolute AC - LDY - Absolute
|
|
80 - STA - Absolute AD - LDA - Absolute
|
|
8E - STX - Absolute AE - LDX - Absolute
|
|
8F - Future Expansion AF - Future Expansion
|
|
90 - BCC B0 - BCS
|
|
91 - STA - (Indirect),Y B1 - LDA - (Indirect),Y
|
|
92 - Future Expansion B2 - Future Expansion
|
|
93 - Future Expansion B3 - Future Expansion
|
|
94 - STY - Zero Page,X B4 - LDY - Zero Page,X
|
|
95 - STA - Zero Page,X BS - LDA - Zero Page,X
|
|
96 - STX - Zero Page,Y B6 - LDX - Zero Page,Y
|
|
97 - Future Expansion B7 - Future Expansion
|
|
98 - TYA B8 - CLV
|
|
99 - STA - Absolute,Y B9 - LDA - Absolute,Y
|
|
9A - TXS BA - TSX
|
|
9B - Future Expansion BB - Future Expansion
|
|
9C - Future Expansion BC - LDY - Absolute,X
|
|
90 - STA - Absolute,X BD - LDA - Absolute,X
|
|
9E - Future Expansion BE - LDX - Absolute,Y
|
|
9F - Future Expansion BF - Future Expansion
|
|
|
|
C0 - Cpy - Immediate E0 - CPX - Immediate
|
|
C1 - CMP - (Indirect,X) E1 - SBC - (Indirect,X)
|
|
C2 - Future Expansion E2 - Future Expansion
|
|
C3 - Future Expansion E3 - Future Expansion
|
|
C4 - CPY - Zero Page E4 - CPX - Zero Page
|
|
C5 - CMP - Zero Page E5 - SBC - Zero Page
|
|
C6 - DEC - Zero Page E6 - INC - Zero Page
|
|
C7 - Future Expansion E7 - Future Expansion
|
|
C8 - INY E8 - INX
|
|
C9 - CMP - Immediate E9 - SBC - Immediate
|
|
CA - DEX EA - NOP
|
|
CB - Future Expansion EB - Future Expansion
|
|
CC - CPY - Absolute EC - CPX - Absolute
|
|
CD - CMP - Absolute ED - SBC - Absolute
|
|
CE - DEC - Absolute EE - INC - Absolute
|
|
CF - Future Expansion EF - Future Expansion
|
|
D0 - BNE F0 - BEQ
|
|
D1 - CMP (Indirect@,Y F1 - SBC - (Indirect),Y
|
|
D2 - Future Expansion F2 - Future Expansion
|
|
D3 - Future Expansion F3 - Future Expansion
|
|
D4 - Future Expansion F4 - Future Expansion
|
|
D5 - CMP - Zero Page,X F5 - SBC - Zero Page,X
|
|
D6 - DEC - Zero Page,X F6 - INC - Zero Page,X
|
|
D7 - Future Expansion F7 - Future Expansion
|
|
D8 - CLD F8 - SED
|
|
D9 - CMP - Absolute,Y F9 - SBC - Absolute,Y
|
|
DA - Future Expansion FA - Future Expansion
|
|
DB - Future Expansion FB - Future Expansion
|
|
DC - Future Expansion FC - Future Expansion
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DD - CMP - Absolute,X FD - SBC - Absolute,X
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DE - DEC - Absolute,X FE - INC - Absolute,X
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DF - Future Expansion FF - Future Expansion
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INSTRUCTION OPERATION
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The following code has been taken from VICE for the purposes of showing
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how each instruction operates. No particular addressing mode is used since
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we only wish to see the operation of the instruction itself.
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src : the byte of data that is being addressed.
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SET_SIGN : sets\resets the sign flag depending on bit 7.
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SET_ZERO : sets\resets the zero flag depending on whether the result
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is zero or not.
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SET_CARRY(condition) : if the condition has a non-zero value then the
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carry flag is set, else it is reset.
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SET_OVERFLOW(condition) : if the condition is true then the overflow
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flag is set, else it is reset.
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SET_INTERRUPT : }
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SET_BREAK : } As for SET_CARRY and SET_OVERFLOW.
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SET_DECIMAL : }
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REL_ADDR(PC, src) : returns the relative address obtained by adding
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the displacement src to the PC.
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SET_SR : set the Program Status Register to the value given.
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GET_SR : get the value of the Program Status Register.
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PULL : Pull a byte off the stack.
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PUSH : Push a byte onto the stack.
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LOAD : Get a byte from the memory address.
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STORE : Store a byte in a memory address.
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IF_CARRY, IF_OVERFLOW, IF_SIGN, IF_ZERO etc : Returns true if the
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relevant flag is set, otherwise returns false.
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clk : the number of cycles an instruction takes. This is shown below
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in situations where the number of cycles changes depending
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on the result of the instruction (eg. Branching instructions).
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AC = Accumulator
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XR = X register
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YR = Y register
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PC = Program Counter
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SP = Stack Pointer
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/* ADC */
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unsigned int temp = src + AC + (IF_CARRY() ? 1 : 0);
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SET_ZERO(temp & 0xff); /* This is not valid in decimal mode */
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if (IF_DECIMAL()) {
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if (((AC & 0xf) + (src & 0xf) + (IF_CARRY() ? 1 : 0)) > 9) temp += 6;
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SET_SIGN(temp);
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SET_OVERFLOW(!((AC ^ src) & 0x80) && ((AC ^ temp) & 0x80));
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if (temp > 0x99) temp += 96;
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SET_CARRY(temp > 0x99);
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} else {
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SET_SIGN(temp);
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SET_OVERFLOW(!((AC ^ src) & 0x80) && ((AC ^ temp) & 0x80));
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SET_CARRY(temp > 0xff);
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}
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AC = ((BYTE) temp);
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/* AND */
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src &= AC;
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SET_SIGN(src);
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SET_ZERO(src);
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AC = src;
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/* ASL */
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SET_CARRY(src & 0x80);
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src <<= 1;
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src &= 0xff;
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SET_SIGN(src);
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SET_ZERO(src);
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STORE src in memory or accumulator depending on addressing mode.
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/* BCC */
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if (!IF_CARRY()) {
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clk += ((PC & 0xFF00) != (REL_ADDR(PC, src) & 0xFF00) ? 2 : 1);
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PC = REL_ADDR(PC, src);
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}
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/* BCS */
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if (IF_CARRY()) {
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clk += ((PC & 0xFF00) != (REL_ADDR(PC, src) & 0xFF00) ? 2 : 1);
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PC = REL_ADDR(PC, src);
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}
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/* BEQ */
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if (IF_ZERO()) {
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clk += ((PC & 0xFF00) != (REL_ADDR(PC, src) & 0xFF00) ? 2 : 1);
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PC = REL_ADDR(PC, src);
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}
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/* BIT */
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SET_SIGN(src);
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SET_OVERFLOW(0x40 & src); /* Copy bit 6 to OVERFLOW flag. */
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SET_ZERO(src & AC);
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/* BMI */
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if (IF_SIGN()) {
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clk += ((PC & 0xFF00) != (REL_ADDR(PC, src) & 0xFF00) ? 2 : 1);
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PC = REL_ADDR(PC, src);
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}
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/* BNE */
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if (!IF_ZERO()) {
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clk += ((PC & 0xFF00) != (REL_ADDR(PC, src) & 0xFF00) ? 2 : 1);
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PC = REL_ADDR(PC, src);
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}
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/* BPL */
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if (!IF_SIGN()) {
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clk += ((PC & 0xFF00) != (REL_ADDR(PC, src) & 0xFF00) ? 2 : 1);
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PC = REL_ADDR(PC, src);
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}
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/* BRK */
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PC++;
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PUSH((PC >> 8) & 0xff); /* Push return address onto the stack. */
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PUSH(PC & 0xff);
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SET_BREAK((1)); /* Set BFlag before pushing */
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PUSH(SR);
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SET_INTERRUPT((1));
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PC = (LOAD(0xFFFE) | (LOAD(0xFFFF) << 8));
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/* BVC */
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if (!IF_OVERFLOW()) {
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clk += ((PC & 0xFF00) != (REL_ADDR(PC, src) & 0xFF00) ? 2 : 1);
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PC = REL_ADDR(PC, src);
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}
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/* BVS */
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if (IF_OVERFLOW()) {
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clk += ((PC & 0xFF00) != (REL_ADDR(PC, src) & 0xFF00) ? 2 : 1);
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PC = REL_ADDR(PC, src);
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}
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/* CLC */
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SET_CARRY((0));
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/* CLD */
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SET_DECIMAL((0));
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/* CLI */
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SET_INTERRUPT((0));
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/* CLV */
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SET_OVERFLOW((0));
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/* CMP */
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src = AC - src;
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SET_CARRY(src < 0x100);
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SET_SIGN(src);
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SET_ZERO(src &= 0xff);
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/* CPX */
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src = XR - src;
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SET_CARRY(src < 0x100);
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SET_SIGN(src);
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SET_ZERO(src &= 0xff);
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/* CPY */
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src = YR - src;
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SET_CARRY(src < 0x100);
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SET_SIGN(src);
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SET_ZERO(src &= 0xff);
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/* DEC */
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src = (src - 1) & 0xff;
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SET_SIGN(src);
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SET_ZERO(src);
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STORE(address, (src));
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/* DEX */
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unsigned src = XR;
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src = (src - 1) & 0xff;
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SET_SIGN(src);
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SET_ZERO(src);
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XR = (src);
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/* DEY */
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unsigned src = YR;
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src = (src - 1) & 0xff;
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SET_SIGN(src);
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SET_ZERO(src);
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YR = (src);
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/* EOR */
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src ^= AC;
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SET_SIGN(src);
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SET_ZERO(src);
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AC = src;
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/* INC */
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src = (src + 1) & 0xff;
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SET_SIGN(src);
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SET_ZERO(src);
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STORE(address, (src));
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/* INX */
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unsigned src = XR;
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src = (src + 1) & 0xff;
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SET_SIGN(src);
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SET_ZERO(src);
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XR = (src);
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/* INY */
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unsigned src = YR;
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src = (src + 1) & 0xff;
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SET_SIGN(src);
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SET_ZERO(src);
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YR = (src);
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/* JMP */
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PC = (src);
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/* JSR */
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PC--;
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PUSH((PC >> 8) & 0xff); /* Push return address onto the stack. */
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PUSH(PC & 0xff);
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PC = (src);
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/* LDA */
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SET_SIGN(src);
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SET_ZERO(src);
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AC = (src);
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/* LDX */
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SET_SIGN(src);
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SET_ZERO(src);
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XR = (src);
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/* LDY */
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SET_SIGN(src);
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SET_ZERO(src);
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YR = (src);
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/* LSR */
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SET_CARRY(src & 0x01);
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src >>= 1;
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SET_SIGN(src);
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SET_ZERO(src);
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STORE src in memory or accumulator depending on addressing mode.
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/* NOP */
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Nothing.
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/* ORA */
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src |= AC;
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SET_SIGN(src);
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SET_ZERO(src);
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AC = src;
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/* PHA */
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src = AC;
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PUSH(src);
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/* PHP */
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src = GET_SR;
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PUSH(src);
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/* PLA */
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src = PULL();
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SET_SIGN(src); /* Change sign and zero flag accordingly. */
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SET_ZERO(src);
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/* PLP */
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src = PULL();
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SET_SR((src));
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/* ROL */
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src <<= 1;
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if (IF_CARRY()) src |= 0x1;
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SET_CARRY(src > 0xff);
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src &= 0xff;
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SET_SIGN(src);
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SET_ZERO(src);
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STORE src in memory or accumulator depending on addressing mode.
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/* ROR */
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if (IF_CARRY()) src |= 0x100;
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SET_CARRY(src & 0x01);
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src >>= 1;
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SET_SIGN(src);
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SET_ZERO(src);
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STORE src in memory or accumulator depending on addressing mode.
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/* RTI */
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src = PULL();
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SET_SR(src);
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src = PULL();
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src |= (PULL() << 8); /* Load return address from stack. */
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PC = (src);
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/* RTS */
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src = PULL();
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src += ((PULL()) << 8) + 1; /* Load return address from stack and add 1. */
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PC = (src);
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/* SBC */
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unsigned int temp = AC - src - (IF_CARRY() ? 0 : 1);
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SET_SIGN(temp);
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SET_ZERO(temp & 0xff); /* Sign and Zero are invalid in decimal mode */
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SET_OVERFLOW(((AC ^ temp) & 0x80) && ((AC ^ src) & 0x80));
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if (IF_DECIMAL()) {
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if ( ((AC & 0xf) - (IF_CARRY() ? 0 : 1)) < (src & 0xf)) /* EP */ temp -= 6;
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if (temp > 0x99) temp -= 0x60;
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}
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SET_CARRY(temp < 0x100);
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AC = (temp & 0xff);
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/* SEC */
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SET_CARRY((1));
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/* SED */
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SET_DECIMAL((1));
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/* SEI */
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SET_INTERRUPT((1));
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/* STA */
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STORE(address, (src));
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/* STX */
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STORE(address, (src));
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/* STY */
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STORE(address, (src));
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/* TAX */
|
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unsigned src = AC;
|
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SET_SIGN(src);
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SET_ZERO(src);
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XR = (src);
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/* TAY */
|
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unsigned src = AC;
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SET_SIGN(src);
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SET_ZERO(src);
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YR = (src);
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/* TSX */
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unsigned src = SP;
|
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SET_SIGN(src);
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SET_ZERO(src);
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XR = (src);
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/* TXA */
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unsigned src = XR;
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SET_SIGN(src);
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SET_ZERO(src);
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AC = (src);
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/* TXS */
|
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unsigned src = XR;
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SP = (src);
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/* TYA */
|
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unsigned src = YR;
|
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SET_SIGN(src);
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SET_ZERO(src);
|
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AC = (src);
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