132 lines
6.3 KiB
Plaintext
132 lines
6.3 KiB
Plaintext
MiniSport Laptop Hacker - Vol 13, 29 Apr 1993
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Copyright(C) 1993 by Brian Mork.
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>>> ADMIN
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No, I'm not superstitious, but the number of this MLH edition did pass my
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mind. The last two weeks, my ZL-2 has been out of commission. Almost si-
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multaneously, I received a letter from n7ftm (Bill) that his is having the
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same trouble. I've spent the last few nights tearing mine apart. Bad for
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me; good for you! I've got more specs on how the power supply works in
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the next edition of MLH.
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In addition, I've been digesting volumes of documentation on Internet and
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Waffle, a BBS program meant to host users and process Internet E-mail and
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Usenet topical forums. I now have a node running on my own computer. See
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the new (and let's hope stable) address below.
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Two people have sent me messages via USMail because something about the
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packet link wasn't getting messages through. Each edition, I try to con-
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firm in the ADMIN section who all I've heard from. If I don't mention
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your callsign here, I didn't get your message. This round I've heard from
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N9ADS, N9LNQ, WA8WZX, W4NTG, W5SYT, N7FTM, KA9CAP.
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>>> COM I/O ARCHITECTURE
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Continuing from Volumes 7,8, and 10, there are only three more registers
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to cover.
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Line Control Register (LCR) at address (BASE+3)
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-----------------------------------------------
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This register allows you to configure the format of the serial data leav-
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ing the UART and (simultaneously) the format expected by the UART. All
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bits of this register are read/write.
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Bit 0&1: These two bits select how many data bits are transferred in each
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asynchronous character. 5,6,7, or 8 bits are selected with values
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of 00,01,10, or 11 respectively. For example, if you desire 7 data
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bits, set Bit0 to 0 and Bit1 to 1.
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Bit 2: Set to 0 if you want one stop bit generated on outbound data and
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checked on inbound data. Setting to 1 chooses 1-1/2 stop bits with
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5-bit data and two stop bits with 6,7, or 8-bit data.
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Bit 3: Set to 1 to generate a parity bit. Set to 0 if you want no parity
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bit at all. If this is set to 0, the next bit has no effect.
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Bit 4: Even Parity Select. When Bit3 is 1 and Bit4 is 0, an odd number of
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1's is transmitted or checked in the data bits and parity bit.
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When Bit3 is a 1 and Bit4 is a 1, an even number of bits is trans-
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mitted or checked.
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Bit 5: When set to 1, the function of Bit4 is reversed.
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Bit 6: Set Break. When this bit is set to 1, the serial output is forced
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to the spacing state (same as data=0) and remains until changing
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this bit to a 0.
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Bit 7: This is the Baud-Rate Divisor Latch Access Bit. This bit is set to
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0 for normal operation allowing access of the transmitter and re-
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ceiver buffers at BASE+0, and the Interrupt Enable Register at
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BASE+1. When set to 1, these same addresses access the Baud Rate
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Divisor.
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Line Status Register (LSR) at address (BASE+5)
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----------------------------------------------
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This register provides information about recent data transfer. All bits
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are not read/write.
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Bit 0: Data Ready. The UART sets this bit to 1 whenever a complete incom-
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ing character is available in the receiver buffer. It is reset to
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0 by writing a zero or by reading the receiver buffer. Bit1
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through Bit4 are "errors" that produce a RLS interrupt (see IER
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and IIR descriptions).
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Bit 1: Overrun. This bit is set to 1 whenever the receiver buffer was not
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read by the CPU before the next character was transferred into the
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receiver buffer (overwriting the lost character). This bit is re-
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set to 0 whenever the CPU reads the LSR.
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Bit 2: Parity Error. If this bit is 1, the received character did not have
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the correct even or odd parity as selected by the bits in the LCR.
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It resets to 0 whenever the CPU reads the LSR.
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Bit 3: Framing Error. This bit is set to 1 whenever the stop bit following
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the last data bit (or parity, if selected) is detected in the spac-
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ing level. (A stop bit is suppose to be mark status.)
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Bit 4: Break Received. This is set to 1 whenever the received data input
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is held in spacing status longer than a full word's time: the total
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of start bit, data bits, parity, and stop bits.
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Bit 5: Transmitter register empty. This bit is 1 when the UART is ready
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to accept a new character for transmission. It actually switches
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to 1 when the previous character is moved from the transmitter
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holding register to the transmit shift register. It becomes 0 con-
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currently with the loading of the holding register by the CPU.
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Bit 6: Transmitter shift register empty. This bit is 1 whenever the shift
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register is idle (nothing being transmitted). It becomes 0 when
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the shift register gets a character from the transmitter holding
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register.
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Bit 7: Permanently 0
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Baud Rate Divisor Latch at addresses (BASE, BASE+1)
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---------------------------------------------------
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These two registers set the bits per second rate transmitted by the UART.
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This is a 16-bit divisor for the clock fed into pin 16 of the 8250 UART,
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giving a frequency *sixteen* times the desired baud rate. Pin 16 is usu-
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ally fed with a frequency of 1.8432 MHz.
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The LSB (least significant byte) is written to (or read from) address
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BASE, and the MSB (most significant byte) is written/read from address
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BASE+1. This is true only when the Divisor Access Bit in the LCR is set
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to 1.
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The following table can be used if a 1.8432 Mhz clock is used (table
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values are decimal):
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300 1200 2400 4800 9600 19200
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MSB 1 0 0 0 0 0
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LSB 128 96 48 24 12 6
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Lastly, a request: Please look in any data book you have and try to iden-
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tify the following three chips. Two of each are surface mounted on the
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bottom side of the ZL power supply switching regulator board. I need to
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find out how they're suppose to work to know if mine are working! A pin-
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out and short description would be GREATLY appreciated!
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73, Brian Mork (Opus-OVH) KA9SNF@wb7nnf.#spokn.wa.usa
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Internet ka9snf@opus-ovh.spk.wa.us
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6006-B Eaker, Fairchild, WA 99011
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