375 lines
20 KiB
Plaintext
375 lines
20 KiB
Plaintext
===============================================================================
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WD65C816 Opcode Reference 02/20/93
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by Eric D. Shepherd
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===============================================================================
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Cycle Time Adjustments
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16A: Add 1 if using 16-bit memory and accumulator
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16B: Add 2 if using 16-bit memory and accumulator
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B: Add 1 if conditional branch is taken
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C: Add 1 if index crosses bank boundary
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D: Add 1 if status register's Decimal bit is set
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I: Add 1 if using 16-bit index registers
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M: Add 7 for each byte copied
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N: Add 1 if in native mode
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P: Add 1 if branch crosses page boundary in emulation mode
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Z: Add 1 if DP is not on a page boundary
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Instruction Hex Cycle Time Status Reg. Notes
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===============================================================================
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ADC #imm 69 2 [16A,D] nv----zc Add memory to A with
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carry.
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ADC abs 6D 4 [16A,D]
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ADC longabs 6F 5 [16A,D]
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ADC dp 65 3 [16A,Z,D]
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ADC (dp) 72 5 [16A,Z,D]
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ADC [dp] 67 6 [16A,Z,D]
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ADC abs,X 7D 4 [16A,C,D]
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ADC abslong,X 7F 5 [16A,D]
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ADC abs,Y 79 4 [16A,C,D]
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ADC dp,X 75 4 [16A,Z,D]
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ADC (dp,X) 61 6 [16A,Z,D]
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ADC (dp),Y 71 5 [16A,Z,C,D]
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ADC [dp],Y 77 6 [16A,Z,D]
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ADC ofs,S 63 4 [16A,D]
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ADC (ofs,S),Y 73 7 [16A,D]
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-------------------------------------------------------------------------------
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AND #imm 29 2 [16A] n-----z- And A with memory.
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AND abs 2D 4 [16A]
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AND abslong 2F 5 [16A]
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AND dp 25 3 [16A,Z]
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AND (dp) 32 5 [16A,Z]
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AND [dp] 27 6 [16A,Z]
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AND abs,X 3D 4 [16A,C]
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AND abslong,X 3F 5 [16A]
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AND abs,Y 39 4 [16A,C]
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AND dp,X 35 4 [16A,Z]
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AND (dp,X) 21 6 [16A,Z]
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AND (dp),Y 31 5 [16A,Z,C]
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AND [dp],Y 37 6 [16A,Z]
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AND ofs,S 23 4 [16A]
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AND (ofs,S),Y 33 7 [16A]
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-------------------------------------------------------------------------------
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ASL 0A 2 n-----zc Shift left memory or A.
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ASL abs 0E 6 [16B]
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ASL dp 06 5 [16B,Z]
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ASL abs,X 1E 7 [16B]
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ASL dp,X 16 6 [16B,Z]
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-------------------------------------------------------------------------------
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BCC relbyte 90 2 [B,P] -------- Branch if carry clear.
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BCS relbyte B0 2 [B,P] -------- Branch if carry set.
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BEQ relbyte F0 2 [B,P] -------- Branch if equal (z=0).
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-------------------------------------------------------------------------------
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BIT #imm 89 2 [16A] ------z- Test memory with bits
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from A.
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BIT abs 2C 4 [16A] nv----z-
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BIT dp 24 3 [16A,Z]
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BIT abs,X 3C 4 [16A,C]
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BIT dp,X 34 4 [16A,Z]
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-------------------------------------------------------------------------------
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BMI relbyte 30 2 [B,P] -------- Branch if minus (n=1).
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BNE relbyte D0 2 [B,P] -------- Branch if not equal.
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BPL relbyte 10 2 [B,P] -------- Branch if positive.
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BRA relbyte 80 2 [P] -------- Branch always.
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-------------------------------------------------------------------------------
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BRK byte 00 7 [N] ----01-- Software break
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BRK 00 ---101-- (sets b in emulation
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mode).
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-------------------------------------------------------------------------------
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BRL relword 82 4 -------- Branch always long.
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BVC relbyte 50 2 [B,P] -------- Branch if overflow
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clear.
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BVS relbyte 70 2 [B,P] -------- Branch if overflow set.
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-------------------------------------------------------------------------------
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CLC 18 2 -------0 Clear carry bit.
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CLD D8 2 ----0--- Clear decimal bit.
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CLI 58 2 -----0-- Clear interrupt disable
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bit.
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CLV B8 2 -0------ Clear overflow bit.
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-------------------------------------------------------------------------------
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CMP #imm C9 2 [16A] n-----zc Compare A with memory.
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CMP abs CD 4 [16A]
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CMP abslong CF 5 [16A]
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CMP dp C5 3 [16A,Z]
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CMP (dp) D2 5 [16A,Z]
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CMP [dp] C7 6 [16A,Z]
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CMP abs,X DD 4 [16A,C]
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CMP abslong,X DF 5 [16A]
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CMP abs,Y D9 4 [16A,C]
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CMP dp,X D5 4 [16A,Z]
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CMP (dp,X) C1 6 [16A,Z]
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CMP (dp),Y D1 5 [16A,Z,C]
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CMP [dp],Y D7 6 [16A,Z]
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CMP ofs,S C3 4 [16A]
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CMP (ofs,S),Y D3 7 [16A]
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-------------------------------------------------------------------------------
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COP byte 02 7 [N] ----01-- Coprocessor enable.
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-------------------------------------------------------------------------------
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CPX #imm E0 2 [I] n-----zc Compare X with memory.
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CPX abs EC 4 [I]
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CPX dp E4 3 [I,Z]
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-------------------------------------------------------------------------------
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CPY #imm C0 2 [I] n-----zc Compare Y with memory.
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CPY abs CC 4 [I]
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CPY dp C4 3 [I,Z]
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-------------------------------------------------------------------------------
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DEC 3A 2 n------c Decrement A or memory.
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DEC abs CE 6 [16B]
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DEC dp C6 5 [16B,Z]
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DEC abs,X DE 7 [16B]
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DEC dp,X D6 6 [16B,Z]
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-------------------------------------------------------------------------------
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DEX CA 2 n------c Decrement X register.
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DEY 88 2 n------c Decrement Y register.
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-------------------------------------------------------------------------------
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EOR #imm 49 2 [16A] n------c Exclusive-OR A with
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memory.
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EOR abs 4D 4 [16A]
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EOR abslong 4F 5 [16A]
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EOR dp 45 3 [16A,Z]
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EOR (dp) 52 6 [16A,Z]
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EOR [dp] 47 6 [16A,Z]
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EOR abs,X 5D 4 [16A,C]
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EOR abslong,X 5F 5 [16A]
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EOR abs,Y 59 4 [16A,C]
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EOR dp,X 55 4 [16A,Z]
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EOR (dp,X) 41 5 [16A,Z]
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EOR (dp),Y 51 6 [16A,Z,C]
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EOR [dp],Y 57 4 [16A,Z]
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EOR ofs,S 43 4 [16A]
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EOR (ofs,S),Y 53 7 [16A]
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-------------------------------------------------------------------------------
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INC 1A 2 n------c Increment A or memory.
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INC abs EE 6 [16B]
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INC dp E6 5 [16B,Z]
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INC abs,X FE 7 [16B]
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INC dp,X F6 6 [16B,Z]
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-------------------------------------------------------------------------------
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INX E8 2 n------c Increment X register.
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INY C8 2 n------c Increment Y register.
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-------------------------------------------------------------------------------
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JMP abs 4C 3 -------- Jump.
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JMP (abs) 6C 5
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JMP (abs,X) 7C 6
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-------------------------------------------------------------------------------
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JML abslong 5C 4 -------- Jump long.
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JML [dp] DC 6
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-------------------------------------------------------------------------------
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JSL abslong 22 8 -------- Jump to subroutine
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long.
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-------------------------------------------------------------------------------
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JSR abs 20 6 -------- Jump to subroutine.
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JSR (addr,X) FC 8
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-------------------------------------------------------------------------------
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LDA #imm A9 2 [16A] n-----z- Load accumulator with
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memory.
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LDA abs AD 4 [16A]
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LDA abslong AF 5 [16A]
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LDA dp A5 3 [16A,Z]
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LDA (dp) B2 5 [16A,Z]
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LDA [dp] A7 6 [16A,Z]
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LDA abs,X BD 4 [16A,C]
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LDA abslong,X BF 5 [16A]
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LDA abs,Y B9 4 [16A,C]
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LDA dp,X B5 4 [16A,Z]
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LDA (dp,X) A1 6 [16A,Z]
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LDA (dp),Y B1 5 [16A,Z,C]
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LDA [dp],Y B7 6 [16A,Z]
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LDA ofs,S A3 4 [16A]
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LDA (ofs,S),Y B3 7 [16A]
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-------------------------------------------------------------------------------
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LDX #imm A2 2 [I] n-----z- Load X register with
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memory.
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LDX abs AE 4 [I]
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LDX dp A6 3 [I,Z]
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LDX abs,Y BE 4 [I,C]
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LDX dp,Y B6 4 [I,Z]
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-------------------------------------------------------------------------------
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LDY #imm A0 2 [I] n-----z- Load Y register with
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memory.
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LDY abs AC 4 [I]
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LDY dp A4 3 [I]
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LDY abs,X BC 4 [I,C]
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LDY dp,X B4 4 [I,Z]
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-------------------------------------------------------------------------------
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LSR 4A 2 n-----zc Logical shift A or
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memory right.
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LSR abs 4E 6 [16A]
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LSR dp 46 5 [16A,Z]
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LSR abs,X 5E 7 [16A]
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LSR dp,X 56 6 [16A,Z]
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-------------------------------------------------------------------------------
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MVN byte,byte 54 [M] -------- Move memory negative
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(srcbank, destbank).
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MVP byte,byte 44 [M] -------- Move memory positive
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(srcbank, destbank).
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* X = source address
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Y = target address
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A = length -1
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-------------------------------------------------------------------------------
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NOP EA 2 -------- No operation.
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-------------------------------------------------------------------------------
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ORA #imm 09 2 [16A] n-----z- Or A with memory.
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ORA abs 0D 4 [16A]
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ORA abslong 0F 5 [16A]
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ORA dp 05 3 [16A,Z]
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ORA (dp) 12 5 [16A,Z]
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ORA [dp] 07 6 [16A,Z]
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ORA abs,X 1D 4 [16A,C]
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ORA abslong,X 1F 5 [16A]
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ORA abs,Y 19 4 [16A,C]
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ORA dp,X 15 4 [16A,Z]
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ORA (dp,X) 01 6 [16A,Z]
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ORA (dp),Y 11 5 [16A,Z,C]
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ORA [dp],Y 17 6 [16A,Z]
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ORA ofs,S 03 4 [16A]
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ORA (ofs,S),Y 13 7 [16A]
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-------------------------------------------------------------------------------
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PEA abs F4 5 -------- Push effective absolute
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address.
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PEI (dp) D4 6 [Z] -------- Push effective indirect
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address.
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PER relword 62 6 -------- Push effective relative
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address.
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PHA 48 3 [16A] -------- Push accumulator.
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PHB 8B 3 -------- Push data bank
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register.
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PHD 0B 4 -------- Push direct page
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register.
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PHK 4B 3 -------- Push program bank
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register.
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PHP 08 3 -------- Push processor status
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register.
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PHX DA 3 [I] -------- Push X register.
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PHY 5A 3 [I] -------- Push Y register.
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-------------------------------------------------------------------------------
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PLA 68 4 [16A] n-----z- Pull accumulator.
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PLB AB 4 n-----z- Pull data bank
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register.
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PLD 2B 5 n-----z- Pull direct page
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register.
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PLP 28 4 nvmxdizc Pull processor status
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register.
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PLX FA 4 [I] n-----z- Pull X register.
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PLY 7A 4 [I] n-----z- Pull Y register.
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-------------------------------------------------------------------------------
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REP #imm C2 3 ???????? Reset processor status
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register bits.
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-------------------------------------------------------------------------------
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ROL 2A 2 n-----zc Rotate A or memory
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right.
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ROL abs 2E 6 [16A]
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ROL dp 26 5 [16A,Z]
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ROL abs,X 3E 7 [16A]
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ROL dp,X 36 6 [16A,Z]
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-------------------------------------------------------------------------------
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RTI 40 6 [N] ???????? Return from interrupt.
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RTI 40 6 ??11???? (emulation mode).
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RTL 6B 6 -------- Return from subroutine
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long.
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RTS 60 6 -------- Return from subroutine.
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-------------------------------------------------------------------------------
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SBC #imm E9 2 [16A,D] nv----zc Subtract memory from
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A with borrow.
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SBC abs ED 4 [16A,D]
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SBC abslong EF 5 [16A,D]
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SBC dp E5 3 [16A,Z,D]
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SBC (dp) F2 5 [16A,Z,D]
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SBC [dp] E7 6 [16A,Z,D]
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SBC abs,X FD 4 [16A,C,D]
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SBC abslong,X FF 5 [16A,D]
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SBC abs,Y F9 4 [16A,C,D]
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SBC dp,X F5 4 [16A,Z,D]
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SBC (dp,X) E1 6 [16A,Z,D]
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SBC (dp),Y F1 5 [16A,Z,C,D]
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SBC [dp],Y F7 6 [16A,Z,D]
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SBC ofs,S E3 4 [16A,D]
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SBC (ofs,S),Y F3 7 [16A,D]
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-------------------------------------------------------------------------------
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SEC 38 2 -------1 Set carry bit.
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SED F8 2 ----1--- Set decimal bit.
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SEI 78 2 -----1-- Set interrupt disable
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bit.
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SEP #imm E2 3 ???????? Set processor status
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register bits.
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-------------------------------------------------------------------------------
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STA abs 8D 4 [16A] -------- Store A to memory.
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STA abslong 8F 5 [16A]
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STA dp 85 3 [16A,Z]
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STA (dp) 92 5 [16A,Z]
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STA [dp] 87 6 [16A,Z]
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STA abs,X 9D 5 [16A]
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STA abslong,X 9F 5 [16A]
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STA abs,Y 99 5 [16A]
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STA dp,X 95 4 [16A,Z]
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STA (dp,X) 81 6 [16A,Z]
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STA (dp),y 91 6 [16A,Z]
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STA [dp],y 97 6 [16A,Z]
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STA ofs,S 83 4 [16A]
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STA (ofs,S),Y 93 7 [16A]
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-------------------------------------------------------------------------------
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STP DB 3 -------- Stop the processor.
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-------------------------------------------------------------------------------
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STX abs 8E 4 [I] -------- Store X register to
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memory.
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STX dp 86 3 [I,Z]
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STX dp,Y 96 4 [I,Z]
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-------------------------------------------------------------------------------
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STY abs 8C 4 [I] -------- Store Y register to
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memory.
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STY dp 84 3 [I,Z]
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STY dp,X 94 4 [I,Z]
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-------------------------------------------------------------------------------
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STZ abs 9C 4 [16A] -------- Store zero to memory.
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STZ dp 64 3 [16A,Z]
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STZ abs,X 9E 5 [16A]
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STZ dp,X 74 4 [16A,Z]
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-------------------------------------------------------------------------------
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TAX AA 2 n-----z- Transfer A to X
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register.
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TAY A8 2 n-----z- Transfer A to Y
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register.
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TCD 5B 2 n-----z- Transfer 16-bit A to
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direct page register.
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TCS 1B 2 -------- Transfer A to stack
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pointer.
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TDC 7B 2 n-----z- Transfer direct page
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register to A.
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-------------------------------------------------------------------------------
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TRB addr 1C 6 [16B] ------z- Test and reset bits
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against A.
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TRB dp 14 5 [16B,Z]
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-------------------------------------------------------------------------------
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TSB addr 0C 6 [16B] ------z- Test and set bits
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against A.
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TSB dp 04 5 [16B,Z]
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-------------------------------------------------------------------------------
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TSC 3B 2 n-----z- Transfer stack pointer
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to A.
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TSX BA 2 n-----z- Transfer stack pointer
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to X register.
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TXA 8A 2 n-----z- Transfer X register to
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A.
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TXS 9A 2 -------- Transfer X register to
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stack pointer.
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TXY 9B 2 n-----z- Transfer X register to
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Y register.
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TYA 98 2 n-----z- Transfer Y register to
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A.
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TYX BB 2 n-----z- Transfer Y register to
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X register.
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-------------------------------------------------------------------------------
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WAI CB 3 -------- Wait for interrupt.
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WDM 42 ? -------- Reserved (currently
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NOP).
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-------------------------------------------------------------------------------
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XBA EB 3 n-----z- Exchange the B and A
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accumulators.
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XCE FB 2 --??---- Exchange carry and
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emulation bits.
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* Append this file to the end of your Shell:SysHelp file.
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* If you find an error, email me at:
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* Internet: uerics@mcl.mcl.ucsb.edu
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* AOL: Sheppy
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