615 lines
25 KiB
Plaintext
615 lines
25 KiB
Plaintext
CMOS Memory Map v1.23 June, 1994
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Compiled from multiple sources by Padgett Peterson
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Corrections/additions/comments to: padgett@tccslr.dnet.mmc.com
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No guarantees of any kind.
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Copyrights/Trademarks belong to whoever they may belong to.
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Found: Algorithm used by IBM in calculating CRC checksums for PS/2
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(see bytes 32h-33h). Complex (recursive part is 12 lines of
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assembly) and not yet validated for every model.
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Background
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The CMOS (complementary metal oxide semiconductor) memory is actually
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a 64 or 128 byte battery-backed RAM memory module that is a part of the
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system clock chip. Some IBM PS/2 models have the capability for a
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2k (2048 byte) CMOS ROM Extension.
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First used with clock-calender cards for the IBM PC-XT, when the PC/AT
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(Advanced Technology) was introduced in 1985, the Motorola MC146818
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became a part of the motherboard. Since the clock only uses fourteen of
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the RAM bytes, the rest are available for storing system configuration data.
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Interestingly, the original IBM-PC/AT (Advanced Technology) standard for
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the region 10h-3Fh is nearly universal with one notable exception: The
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IBM PS/2 systems deviate considerably (Note: AMSTRAD 8086 machines were
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among the first to actively use the CMOS memory available and since they
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*predate* the AT, do not follow the AT standard).
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This is just another example of how IBM created a standard, lost control
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of it, tried to replace it, failed and lost market share in the process.
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Originally, the IBM PC/AT only made use of a small portion of CMOS memory
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and was defined in the IBM PC/AT Technical Reference Manual, specifically
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bytes 10h, 12h, 14h-18h, 2Eh-33h. The balance was left undefined but was
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quickly appropriated by various BIOS manufacturers for such user-selectable
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options such as wait states, clock speeds, initial boot drive selection, and
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password storage.
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Later, as CMOS memory requirements grew, newer clock chips with 128
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bytes of RAM came into use. However the fact remains that once the AT
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standard was established, only IBM has tried to change the definitions
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of that first description.
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Accessing the CMOS
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The CMOS memory exists outside of the normal address space and cannot
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contain directly executable code. It is reachable through IN and OUT
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commands at port number 70h (112d) and 71h (113d). To read a CMOS byte,
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an OUT to port 70h is executed with the address of the byte to be read and
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an IN from port 71h will then retrieve the requested information. The
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following BASIC fragment will read 128 CMOS bytes and print them to the
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screen in 8 rows of 16 values.
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CMOS RAM space has an upper limit of 128 bytes because of the structure
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of port 70: only bits 0-6 are used for addressing, bit 7 is used to
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enable (0) or disable (1) Non-Maskable Interrupts (NMI) and explains why
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IBM uses 80h OR <address> to read/write data & follows with a "throw-away"
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call.
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Note that if the CMOS only has 64 bytes available, addressing will
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generally wrap and addresses from 40h-7Fh will mirror 00h-3Fh. Output will
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be hexadecimal.
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10 CLS
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20 FOR i = 0 TO &H7F
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30 OUT &H70, i
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40 PRINT USING "\ \"; HEX$(INP(&H71));
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50 NEXT i
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60 PRINT " "
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Note: where not otherwise noted, all data points are expressed as BYTES
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these are eight bit values and are read from MSB to LSB e.g.
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0000 0000 0101 1010 binary would be written as 5Ah
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7654 3210 where only some bits are used this is represented with
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Xs e.g bits 5-3 would be shown as 00xx x000
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Organization of CMOS Memory - Clock
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00h-0Eh is defined by the clock hardware and all must follow it. Other
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manufacturers generally follow the same format as specified for the
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region 10h - 2Fh. Some also follow the IBM format for 30h-33h but not all
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(Zenith in particular is different).
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The first fourteen bytes are dedicated to the MC146818 chip clock functions
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and consist of ten read/write data registers and four status registers, two
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of which are read/write and two of which are read only.
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The format of the ten clock data registers (bytes 00h-09h) is:
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00h Seconds (BCD 00-59, Hex 00-3B) Note: Bit 7 is read only
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01h Second Alarm (BCD 00-59, Hex 00-3B)
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02h Minutes (BCD 00-59, Hex 00-3B))
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03h Minute Alarm (BCD 00-59, Hex 00-3B)
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04h Hours (BCD 00-23, Hex 00-17 if 24 hr mode)
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(BCD 01-12, Hex 01-0C if 12 hr am)
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(BCD 81-92. Hex 81-8C if 12 hr pm)
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05h Hour Alarm (same as hours)
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06h Day of Week (01-07 Sunday=1)
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07h Date of Month (BCD 01-31, Hex 01-1F)
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08h Month (BCD 01-12, Hex 01-0C)
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09h Year (BCD 00-99, Hex 00-63)
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BCD/Hex selection depends on Bit 2 of register B (0Bh)
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12/24 Hr selection depends on Bit 1 of register B (0Bh)
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Alarm will trigger when contents of all three Alarm byte registers
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match their companions.
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The following is the on-chip status register information.
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0Ah Status Register A (read/write) (usu 26h)
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Bit 7 - (1) time update cycle in progress, data ouputs undefined
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(bit 7 is read only)
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Bit 6,5,4 - 22 stage divider. 010b - 32.768 Khz time base (default)
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Bit 3-0 - Rate selection bits for interrupt.
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0000b - none
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0011b - 122 microseconds (minimum)
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1111b - 500 milliseconds
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0110b - 976.562 microseconds (default)
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0Bh Status Register B (read/write)
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Bit 7 - 1 enables cycle update, 0 disables
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Bit 6 - 1 enables periodic interrupt
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Bit 5 - 1 enables alarm interrupt
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Bit 4 - 1 enables update-ended interrupt
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Bit 3 - 1 enables square wave output
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Bit 2 - Data Mode - 0: BCD, 1: Binary
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Bit 1 - 24/12 hour selection - 1 enables 24 hour mode
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Bit 0 - Daylight Savings Enable - 1 enables
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0Ch Status Register C (Read only)
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Bit 7 - Interrupt request flag - 1 when any or all of bits 6-4 are
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1 and appropriate enables (Register B) are set to 1. Generates
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IRQ 8 when triggered.
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Bit 6 - Periodic Interrupt flag
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Bit 5 - Alarm Interrupt flag
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Bit 4 - Update-Ended Interrupt Flag
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Bit 3-0 ???
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0Dh Status Register D (read only)
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Bit 7 - Valid RAM - 1 indicates batery power good, 0 if dead or
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disconnected.
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Bit 6-0 ???
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---------------------------------------------
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Organization of CMOS Memory - non-Clock
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The last two bytes in the first hexadecimal decade (hexade ?) were not
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specified in the PC/AT but may have the following use on some systems:
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0Eh (PS/2) Diagnostic Status Byte
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Bit 7 - When set (1) indicates clock has lost power
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Bit 6 - (1) indicates incorrect checksum
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Bit 5 - (1) indicates that equipment configuration is incorrect
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power-on check requires that atleast one floppy be installed
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Bit 4 - (1) indicates error in memory size
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Bit 3 - (1) indicates that controller or disk drive failed initialization
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Bit 2 - (1) indicates that time is invalid
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Bit 1 - (1) indicates installed adaptors do not match configuration
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Bit 0 - (1) indicates a time-out while reading adaptor ID
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0Eh (AMSTRAD) 6 BYTEs time and date machine last used
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0Fh Reset Code
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(IBM PS/2 "Shutdown Status Byte")
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---------------------------------------------
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The second group of values extends from address 10h to 2Dh. The word at
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2Eh-2Fh is a byte-wise summation of the values in these bytes. Most BIOSes
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will generate a CMOS Checksum error if this value is invalid however many
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programs ignore the checksum and report the apparent value. The current
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version of MSD reports my XT as having 20+ MB of extended memory.
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Where a definiton appears universal, no identification is made. Where
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the definition is thought to be specific to a manufacturer/model (AMI,
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AMSTRAD, IBM AT, IBM PS/2) the identification is enclosed in parens. The
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AMSTAD definitions appear to relate to 8088/8086 (PC and PC/XT class)
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mchines only. AT class machines appear to adhere to IBM PC/AT fornat.
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---------------------------------------------
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10h - Floppy Drive Type
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Bits 7-4 - First Floppy Disk Drive Type
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0h No Drive
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1h 360 KB 5 1/4 Drive
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2h 1.2 MB 5 1/4 Drive - note: not listed in PS/2 technical manual
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3h 720 KB 3 1/2 Drive
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4h 1.44 MB 3 1/2 Drive
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5h-Fh unused (??? 5h: 2.88 Mb 3 1/2 Drive ???)
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Bits 3-0 Second Floppy Disk Drive Type (bit settings same as A)
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Hence a PC having a 5 1/4 1.2 Mb A: drive and a 1.44 Mb B: drive will
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have a value of 24h in byte 10h. With a single 1.44 drive: 40h.
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---------------------------------------------
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11h - (IBM-PS/2) First Fixed Disk Drive Type Byte (00-FFh) Note: if IBM
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ESDI or SCSI drive controller is used, CMOS drive type will be zero (00 -
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no drive) and Int 13h will be directed to controller ROM.
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11h - (AMI) Keyboard Typematic Data
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Bit 7 Enable Typematic (1 = On)
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Bits 6-5 Typematic Delay (wait before begin repeating)
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00b 250 ms
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01b 500 ms
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10b 750 ms
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11b 100 ms
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Bits 4-0 Typematic Rate char/sec e.g. 01010b = 12.0 cps
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00000b - 300 01000b - 159 10000b - 75 11000b - 37
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00001b - 267 01001b - 133 10001b - 67 11001b - 33
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00010b - 240 01010b - 120 10010b - 60 11010b - 30
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00011b - 218 01011b - 109 10011b - 55 11011b - 27
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00100b - 200 01100b - 100 10100b - 50 11100b - 25
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00101b - 185 01101b - 92 10101b - 46 11101b - 23
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00110b - 171 01110b - 86 10110b - 43 11110b - 21
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00111b - 160 01111b - 80 10111b - 40 11111b - 20
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11h - (AMI) Advanced Setup Options
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bit 7 mouse enabled
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bit 6 test memory above 1 megabyte
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bit 5 generate clicks during memory test
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bit 4 enable memory parity check
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bit 3 display key for Setup while booting
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bit 2 store user-defined disk data at top of memory instead of 0030h:0000h
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bit 1 request F1 keypress on boot error
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---------------------------------------------
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12h - (IBM PS/2) Second Fixed Disk Drive Type (00-FFh) - see 11h
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12h - Hard Disk Data
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Bits 7-4 First Hard Disk Drive
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00 No drive
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01-0Eh Hard drive Type 1-14
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0Fh Hard Disk Type 16-255 (actual Hard Drive Type is in CMOS RAM 1Ah)
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Bits 3-0 Second Hard Disk Drive Type (same as above except extrnded type
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will be found in 1Bh).
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A PC with a single type 2 (20 Mb ST-225) hard disk will have 20h in byte 12h
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Note: some PCs utilizing external disk controller ROMs will use type 0 to
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disable ROM BIOS (e.g. Zenith 248 with Plus HardCard).
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---------------------------------------------
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13h (AMI) Advanced Setup Options
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Bit 7 Mouse Enabled (1 = On)
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Bit 6 Test Memory above 1 MB (1 = On)
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Bit 5 Memory Test Tick Sound (1 = On)
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Bit 4 Memory Parity Error Check (1 = On)
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Bit 3 Press <Esc> to Disable Memory Test (1 = On)
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Bit 2 User-Defined Hard Disk (1 = Type 47 data area at address 0:300h)
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Bit 1 Wait for <F1> Message if Error (1 = On)
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Bit 0 Turn Num Lock On at boot (1 = On)
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13h (PS/2 MCA) internal POST operations
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bit 7 POST sets VGA pel information
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bit 6 RTC battery OK
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bit 5 invoke ROM BASIC from POST
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bit 4 POST sets typematic to 30cps/250ms delay instead of 10.9cps/500ms
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bit 3-2 unused or unknown
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bit 1 network password installed
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bit 0 power-on password installed
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---------------------------------------------
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14h - Equipment Byte
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Bits 7-6 Number of Floppy Drives (system must have at least one)
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00b 1 Drive
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01b 2 Drives
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10b ??? 3 Drives
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11b ??? 4 Drives
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Bits 5-4 Monitor Type
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00b Not CGA or MDA (observed for EGA & VGA)
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01b 40x25 CGA
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10b 80x25 CGA
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11b MDA (Monochrome)
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Bit 3 Display Enabled (1 = On) (turned off to enable boot of rackmount)
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Bit 2 Keyboard Enabled (1 = On) (turned off to enable boot of rackmount)
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Bit 1 Math coprocessor Installed (1 = On)
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Bit 0 Floppy Drive Installed (1 = On) (turned off for rackmount boot)
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14h - (AMSTRAD) BYTE user RAM checksum
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LSB of sum of all user bytes should be AAh
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---------------------------------------------
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15h - Base Memory in K, Low Byte
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15h - (AMSTRAD) WORD Enter key scancode/ASCII code
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default: 1C0Dh - emulates Return key
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---------------------------------------------
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16h Base Memory in K, High Byte
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The value in 15h-16h should be the same as in 0:413h and that returned by
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Int 12h. A PC having 640k (280h) of conventional memory will return 80h in
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byte 15h and 02h in byte 16h.
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---------------------------------------------
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17h - Extended Memory in K, Low Byte
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17h - (AMSTRAD) WORD Forward delete key scancode/ASCII code
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default: 2207h - emulates ^G (bell/beep)
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---------------------------------------------
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18h - Extended Memory in K, High Byte (some systems will only accommodate
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15 Mb extended or 16 Mb total) Format is the same as in 15h-16h
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---------------------------------------------
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19h - First Extended Hard Disk Drive Type (not in original AT
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specification but now nearly universally used except for PS/2).
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0-Fh unused (would not require extension. Note: this has the effect
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making type 0Fh (15d) unavailable.
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10h-FFh First Extended Hard Drive Type 16d-255d
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19h - (MCA) Slot 0 adapter card ID
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For most manufacturers the last drive type (typically either 47d or 49d)
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is "user defined" and parameters are stored elsewhere in the CMOS.
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19h - (AMSTRAD) WORD Joystick fire button 1 scancode/ASCII code
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default: FFFFh - (no translation)
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---------------------------------------------
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1Ah - Second Extended Hard Disk Drive Type (see 19h above)
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1Ah - (MCA) Slot 0 adapter card ID
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---------------------------------------------
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1Bh - (MCA) Slot 1 adapter card ID
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1Bh - (AMI) First Hard Disk (type 47) user defined: # of Cylinders, LSB
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1Bh - (AMSTRAD) WORD Joystick fire button 2 scancode/ASCII code
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default: FFFFh - (no translation)
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1Bh - (PHOENIX) LSB of Word to 82335 RC1 roll compare register
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---------------------------------------------
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1Ch - (MCA) Slot 1 adapter card ID
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1Ch - (AMI) First Hard Disk user defined: # of Cylinders, High Byte
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1Ch - (PHOENIX) MSB of Word to 82335 RC1 roll compare register
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---------------------------------------------
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1Dh - (MCA) Slot 2 adapter card ID
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1Dh - (AMI) First Hard Disk user defined: Number of Heads
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1Dh - (AMSTRAD) WORD mouse button 1 scancode/ASCII code
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default: FFFFh - (no translation)
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1Dh - (Zenith Z-200 monitor) Boot Drive Selection
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Bits 6-5 (0xx0 0000)
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00 - MFM Monitor
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01 - First floppy drive (A:)
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10 - First fixed disk (C:)
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11 - First floppy drive (A:). If not there then First fixed disk (C:)
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(this is the default).
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1Dh - (PHOENIX) LSB of Word to 82335 RC2 roll compare register
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---------------------------------------------
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1Eh - (MCA) Slot 2 adapter card ID
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1Eh - (AMI) First Hard Disk user defined: Write Precompensation Cylinder,
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Low Byte
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1Eh - (PHOENIX) MSB of Word to 82335 RC2 roll compare register
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---------------------------------------------
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1Fh - (MCA) Slot 3 adapter card ID
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1Fh - (AMI) First Hard Disk user defined: Write Precompensation Cylinder,
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High Byte
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1Fh - (AMSTRAD) WORD mouse button 2 scancode/ASCII code
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default: FFFFh - (no translation)
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---------------------------------------------
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20h - (MCA) Slot 3 adapter card ID
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20h - (AMI) First Hard Disk user defined: Control Byte
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bits 7-6 no retries (1)
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bit 5 bad sector map at last cylinder+1
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bit 4 unused (0)
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bit 3 more than 8 heads
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bits 2-0 unused (0)
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20h - (PHOENIX) First user defined hard disk (type 48) Cylinders LSB
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---------------------------------------------
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21h - (MCA) Programmable Option Select configuration byte 2
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21h - (AMI) First Hard Disk user defined: Landing Zone, Low Byte
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21h - (AMSTRAD) BYTE mouse X scaling factor, default: 0Ah
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21h - (PHOENIX) First user defined hard disk (type 48) Cylinders MSB
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---------------------------------------------
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22h - (MCA) Programmable Option Select configuration byte 3
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22h - (AMI) First Hard Disk user defined: Landing Zone, High Byte
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22h - (AMSTRAD) BYTE mouse Y scaling factor default: 0Ah
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22h - (PHOENIX) First user defined hard disk (type 48) of Heads
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---------------------------------------------
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23h - (MCA) Programmable Option Select configuration byte 4
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23h - (AMI) First Hard Disk user defined: # of Sectors per track
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23h - (AMSTRAD) BYTE initial VDU mode and drive count default: 20h
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bit 7: enables extended serial flow control
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(NB this is buggy)
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bit 6: set if two floppy drives installed
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bits 5 & 4: (from Amstrad 1640 tech ref)
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0 0 Internal video adapter
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0 1 CGA card added; 40 x 25 mode
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1 0 CGA card added; 80 x 25 mode
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1 1 mono card added; 80 x 25 mode
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23h - (PHOENIX) First user defined hard disk (type 48) Write Precomp. LSB
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---------------------------------------------
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24h - (MCA) Programmable Option Select configuration byte 5
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24h - (AMI) Second Hard Disk user defined: # of Cylinders, Low Byte
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24h - (AMSTRAD) BYTE initial VDU character attribute, default: 7h
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24h - (PHOENIX) First user defined hard disk (type 48) Write Precomp. MSB
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---------------------------------------------
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25h - (AMI) Second Hard Disk user defined: # of Cylinders, High Byte
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25h - (AMSTRAD) BYTE size of RAM disk in 2K blocks
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default: 0 - only used by the RAMDISK software supplied.
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25h - (PHOENIX) First user defined hard disk (type 48) Parking zone LSB
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---------------------------------------------
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26h - (AMI) Second Hard Disk user defined: Number of Heads
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26h - (AMSTRAD) BYTE initial system UART setup byte
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default: E3h - format as for Int 14h fn 0
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26h - (PHOENIX) First user defined hard disk (type 48) Parking zone MSB
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---------------------------------------------
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27h - (AMI) Second Hard Disk user defined: Write Precompensation Cylinder,
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Low Byte
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27h - (AMSTRAD) BYTE initial external UART setup byte
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default: E3h - format as for Int 14h fn 0
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27h - (PHOENIX) First user defined hard disk (type 48) Sectors per track
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---------------------------------------------
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28h - (AMI) Second Hard Disk user defined: Write Precompensation Cylinder,
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High Byte
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28h - (HP Vectra) checksum over words 29h-2Dh
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28h-3Fh (AMSTRAD) 24 BYTEs user applications default: zeroes
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---------------------------------------------
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29h - (AMI) Second Hard Disk user defined: Control Byte (80h if # of heads
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is equal or greater than 8)
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29h - (PHOENIX) LSB word to Intel 82335 CC0 compare register
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---------------------------------------------
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2Ah - (AMI) Second Hard Disk user defined: Landing Zone, Low Byte
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2Ah - (PHOENIX) MSB word to Intel 82335 CC0 compare register
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---------------------------------------------
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2Bh - (AMI) Second Hard Disk user defined: Landing Zone, High Byte
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2Bh - (PHOENIX) LSB word to Intel 82335 CC1 compare register
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---------------------------------------------
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2Ch - (AMI) Second Hard Disk user defined: # of Sectors per track
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2Ch - (COMPAQ) bit 6: 0 - numlock OFF on boot, 1 - numlock ON at boot
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2Ch - (PHOENIX) MSB word to Intel 82335 CC1 compare register
|
|
|
|
---------------------------------------------
|
|
2Dh - (AMI) Configuration Options
|
|
Bit 7 Weitek Installed(1 = On)
|
|
Bit 6 Floppy Drive Seek - turn off for fast boot
|
|
Bit 5 Boot Order 0 - Drive C:, then A:
|
|
1 - Drive A:, then C:
|
|
Bit 4 Boot Speed (0 - Low; 1 - High)
|
|
Bit 3 External Cache Enable (1 = On)
|
|
Bit 2 Internal Cache Enable (1 = On)
|
|
Bit 1 Use Fast Gate A20 after boot (1 = On)
|
|
Bit 0 Turbo Switch (1 = On)
|
|
2Dh - (PHOENIX) Checks for values AAh or CCh
|
|
|
|
---------------------------------------------
|
|
2Eh - Standard CMOS Checksum, High Byte
|
|
2Fh - Standard CMOS Checksum, Low Byte
|
|
|
|
2Eh and 2Fh are as defined by the original IBM PC/AT specification and
|
|
represent a byte-wise additive sum of the values in locations 10h-2Dh only,
|
|
00h-0Fh and 30h-33h are not included. This definition is used by most
|
|
clone manufacturers including AMI, Compaq, Tandon, NEC, and Zenith. The
|
|
IBM PS/2 line does not follow this standard with the range 19h-31h being
|
|
undefined.
|
|
|
|
---------------------------------------------
|
|
30h - Extended Memory in K, Low Byte
|
|
|
|
---------------------------------------------
|
|
31h - Extended Memory in K, High Byte
|
|
(??? this appears to mirror the value in bytes 17h-18h.)
|
|
|
|
---------------------------------------------
|
|
32h - Century Byte (BCD value for the century - currently 19)
|
|
32h - (IBM-PS2) Configuration CRC low byte. CRC for range 10h-31h
|
|
|
|
---------------------------------------------
|
|
33h - Information Flag
|
|
Bit 7 128K (??? believe this indicates the presence of the special 128k
|
|
memory expansion board for the AT to boost the "stock" 512k
|
|
to 640k - all machines surveyed have this bit set)
|
|
Bits 6-0 ???
|
|
33h - (IBM PS/2) Configuration CRC high byte (see entry for 32h)
|
|
33h - (PHOENIX) Bit 4 (000x 0000) bit 4 from Intel CPU register CP0
|
|
|
|
---------------------------------------------
|
|
34h - (AMI) Shadowing & Boot Password
|
|
Bits 7-6 Password Selection
|
|
00b Disable 10b Reserved
|
|
01b Set 11b Boot
|
|
Bit 5 C8000h Shadow ROM (Bit 1 = On)
|
|
Bit 4 CC000h Shadow ROM (Bit 1 = On)
|
|
Bit 3 D0000h Shadow ROM (Bit 1 = On)
|
|
Bit 2 D4000h Shadow ROM (Bit 1 = On)
|
|
Bit 1 D8000h Shadow ROM (Bit 1 = On)
|
|
Bit 0 DC000h Shadow ROM (Bit 1 = On)
|
|
|
|
---------------------------------------------
|
|
35h - (AMI) Shadowing
|
|
Bit 7 E0000h Shadow ROM (Bit 1 = On)
|
|
Bit 6 E4000h Shadow ROM (Bit 1 = On)
|
|
Bit 5 E8000h Shadow ROM (Bit 1 = On)
|
|
Bit 4 EC000h Shadow ROM (Bit 1 = On)
|
|
Bit 3 F0000h Shadow ROM (Bit 1 = On)
|
|
Bit 2 C0000h Shadow ROM (Bit 1 = On)
|
|
Bit 1 C4000h Shadow ROM (Bit 1 = On)
|
|
Bit 0 Reserved
|
|
35h - (PHOENIX) Second user defined hard disk (type 48) Cylinders LSB
|
|
NOTE: used only when PS/2 style password is NOT in effect.
|
|
|
|
---------------------------------------------
|
|
36h - (PHOENIX) Second user defined hard disk (type 48) Cylinders MSB
|
|
NOTE: used only when PS/2 style password is NOT in effect.
|
|
|
|
---------------------------------------------
|
|
37h - (IBM PS/2) Date Century Byte
|
|
37h - (PHOENIX) Second user defined hard disk (type 48) # of heads
|
|
NOTE: used only when PS/2 style password is NOT in effect.
|
|
|
|
---------------------------------------------
|
|
38h-3Dh (AMI) Encrypted Password
|
|
|
|
38h-3Fh ??? (IBM PS/2) Encrypted Password. Initialized to 00h in all
|
|
bytes. Will accept from 1-7 scan codes.
|
|
|
|
38h - (PHOENIX) Second user defined hard disk (type 48) Write Precomp. LSB
|
|
NOTE: used only when PS/2 style password is NOT in effect.
|
|
|
|
39h - (PHOENIX) Second user defined hard disk (type 48) Write Precomp. MSB
|
|
NOTE: used only when PS/2 style password is NOT in effect.
|
|
|
|
3Ah - (PHOENIX) Second user defined hard disk (type 48) Parking Zone LSB
|
|
NOTE: used only when PS/2 style password is NOT in effect.
|
|
|
|
3Bh - (PHOENIX) Second user defined hard disk (type 48) Parking Zone MSB
|
|
NOTE: used only when PS/2 style password is NOT in effect.
|
|
|
|
3Ch - (PHOENIX) Second user defined hard disk (type 48) Sectors per track
|
|
NOTE: used only when PS/2 style password is NOT in effect.
|
|
|
|
3Eh - (AMI) Extended CMOS Checksum, High Byte (includes 34h - 3Dh)
|
|
|
|
3Fh - (AMI) Extended CMOS Checksum, Low Byte (includes 34h - 3Dh)
|
|
|
|
---------------------------------------------
|
|
|
|
End of original 64 CMOS RAM bytes. Many modern chips now contain 128
|
|
bytes and the IBM PS/2 has provision for 2k of "Expansion CMOS".
|
|
The AMI HI-FLEX description is below. If the chip does have only
|
|
64 bytes, addresses will wrap so that requests for bytes 40h-7Fh will
|
|
return the same values as 00h-3Fh.
|
|
|
|
40h ???
|
|
|
|
41h - (AMI)
|
|
Bits 7-6 IOR/IOW Wait states
|
|
Bits 5-4 16-bit DMA Wait States
|
|
Bits 3-2 8-bit DMA Wait States
|
|
Bit 1 EMR bit
|
|
Bit 0 DMA Clock Source
|
|
|
|
42h-43h ???
|
|
|
|
44h - (AMI)
|
|
Bit 4 NMI Power Fail Warning
|
|
Bit 3 NMI Local Bus Timeout
|
|
|
|
45h - (AMI)
|
|
Bits 7-6 AT Bus 32-Bit Delay
|
|
Bits 5-4 AT Bus 16-Bit Delay
|
|
Bits 3-2 AT Bus 8-Bit Delay
|
|
Bits 1-0 AT Bus I/O Delay
|
|
|
|
46h - (AMI)
|
|
Bits 7-6 AT Bus 32 Bit Wait States
|
|
Bits 5-4 AT Bus 16 Bit Wait States
|
|
Bits 3-2 AT Bus 8 Bit Wait States
|
|
Bits 1-0 AT Bus Clock Source
|
|
|
|
47h - 50h ???
|
|
|
|
51h - (AMI)
|
|
Bit 7 Bank 0/1 RAS Precharge
|
|
Bit 6 Bank 0/1 Access Wait States
|
|
Bits 3-2 Bank 0/1 Wait States
|
|
|
|
52h ???
|
|
|
|
53h - (AMI)
|
|
Bit 7 Bank 2/3 RAS Precharge
|
|
Bit 6 Bank 2/3 Access Wait States
|
|
Bits 3-2 Bank 2/3 Wait States
|
|
|
|
54h-7Fh ???
|
|
|
|
|
|
Revision History
|
|
|
|
v1.23 June, 1994 Added some MCA info from _The_Undocumented_PC_
|
|
v1.22 Feb, 1994 Added NMI mask note
|
|
v1.21 Jan, 1994 Added note for PS/2 checksum found
|
|
v1.20 Sept, 1993 PHOENIX data from Wim Osterholt added
|
|
additional AMI data from Howie (hjh@gwd.dst.gov.au)
|
|
v1.15 June, 1993 AMSTRAD data updated
|
|
v1.1 June, 1993 AMSTRAD & PS/2 data added
|
|
v1.0 June, 1993 First release: Motorola MC 146818, PC-AT & AMI
|
|
"Hi-Flex" information baselined
|