241 lines
15 KiB
Plaintext
241 lines
15 KiB
Plaintext
----------------------------------------------------------------
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| Digital Equipment Corporation |
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| L SSSSS III 1 1 |
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| L S S I 11 11 |
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| L S I 1 1 |
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| L SSSSS I XXX 1 1 |
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| L S I 1 1 |
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| L S S I 1 1 |
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| LLLLLLL SSSSS III 111 111 |
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| LSI-11 MICROPROCESSOR Instruction Set Summary |
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|XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX|
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|XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX|
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|XXXXX X XXX XXX XXXXXXXX XXX XXX XX XXXX XXXXXXXX XXX XXX|
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|XXXXX X XXXXXXXX XXXXXXXX XXXXXXXX XX XXXX XXXXXXXX XXX XXX|
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|XX X XXX XXX XX XX XXX XXX X XXX XX XX XXX XXX|
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|X XX X XXX XXX X XX X XXX XXX XX XXXX XXXXX X XXX XXX|
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|X XX X XXX XXX X XX X XXX XXX XX XXXX XX X XXX XXX|
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|X XX X XXX XXX X XX X XXX XXX XX XXXX X XX X XXX XXX|
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|XX X XXX XXX XX X XXX XXX XXX XX XX X XXX XXX|
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|XXXXXXXX XXXXXXXX XXXXX X XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX|
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|XXXXXXXX XXXXXXXX XX XX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX|
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|XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX|
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|Written by Jonathan Bowen |
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| Programming Research Group |
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| Oxford University Computing Laboratory |
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| 8-11 Keble Road |
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| Oxford OX1 3QD |
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| England |
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| Tel +44-865-273840 |
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|Created August 1981 |
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|Updated April 1985 |
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|Issue 1.1 Copyright (C) J.P.Bowen 1985|
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----------------------------------------------------------------
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----------------------------------------------------------------
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|Mnemonic |Opcode|NZVC|Description |Notes |
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|---------+------+----+--------------------------+-------------|
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|ADCb d |B055DD|****|Add Carry |d=d+C |
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|ADD s,d |06SSDD|****|Add |d=s+d |
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|ASH s,r |072RSS|****|Arithmetic Shift |r=r*2^s (EIS)|
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|ASHC s,r |073RSS|****|Arithmetic Shift Combined | (EIS)|
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|ASLb d |B063DD|****|Arithmetic Shift Left |d=d*2 |
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|ASRb d |B062DD|****|Arithmetic Shift Right |d=d/2 |
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|BCC a |1030XX|----|Branch if Carry Clear |If C=0 |
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|BCS a |1034XX|----|Branch if Carry Set |If C=1 |
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|BEQ a |0014XX|----|Branch if Equal |If Z=0 |
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|BGE a |0020XX|----|Branch if Greater or Equal|If NxV=0 |
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|BGT a |0030XX|----|Branch if Greater Than |If Zv{NxV}=0 |
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|BICb s,d |B4SSDD|**0-|Bit Clear |d=d&{~s} |
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|BISb s,d |B5SSDD|**0-|Bit Set (OR) |d=dvs |
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|BITb s,d |B3SSDD|**0-|Bit Test (AND) |d&s |
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|BHI a |1010XX|----|Branch if Higher |If CvZ=0 |
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|BHIS a |1030XX|----|Branch if Higher or Same |If C=0 |
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|BLE a |0034XX|----|Branch if Less or Equal |If Zv{NxV}=1 |
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|BLT a |0024XX|----|Branch if Less Than |If NxV=1 |
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|BLO a |1034XX|----|Branch if Lower |If C=1 |
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|BLOS a |1014XX|----|Branch if Lower or Same |If CvZ=1 |
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|BMI a |1004XX|----|Branch if Minus |If N=1 |
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|BNE a |0010XX|----|Branch if Not Equal |If Z=1 |
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|BPL a |1000XX|----|Branch if Plus |If N=0 |
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|BPT |000003|----|Breakpoint Trap |Vector at 14 |
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|BR a |0004XX|----|Branch |PC=PC+2*XX |
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|BVC a |1020XX|----|Branch if Overflow Clear |If V=0 |
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|BVS a |1024XX|----|Branch if Overflow Set |If V=1 |
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|CALL d |0047DD|----|Call subroutine | (= JSR PC,d)|
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|CCC |000257|0000|Clear all Condition Codes |{C,N,V,Z}=0 |
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|CLC |000241|---0|Clear Carry |C=0 |
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|CLN |000250|0---|Clear Negative |N=0 |
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|CLRb d |B050DD|0100|Clear |d=0 |
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|CLV |000242|--0-|Clear Overflow |V=0 |
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|CLZ |000244|-0--|Clear Zero |Z=0 |
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|CMPb s,d |B2SSDD|****|Compare |s-d |
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|COMb d |B051DD|**01|Complement |d=~d |
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|DECb d |B053DD|***-|Decrement |d=d-1 |
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|DIV s,r |071RSS|****|Divide |r=r/s (EIS)|
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|EMT t |1040TT|----|Emulator Trap |Vector at 30 |
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|FADD r |07500R|**00|Floating Add | (FIS)|
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|FDIV r |07503R|**00|Floating Divide | (FIS)|
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|FMUL r |07502R|**00|Floating Multiply | (FIS)|
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|FSUB r |07501R|**00|Floating Subtract | (FIS)|
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|HALT |000000|----|Halt | |
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|INCb d |B052DD|***-|Increment |d=d+1 |
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|IOT |000004|----|Input/Output Trap |Vector at 20 |
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|JMP d |0001DD|----|Jump |PC=d |
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|JSR r,d |004RDD|----|Jump to Subroutine |r=PC,PC=d |
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|MARK n |0064NN|----|Mark stack |RTS aid |
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|MFPS d |1067DD|**0-|Move From Processor Status|d=PS (byte)|
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|MOVb s,d |B1SSDD|**0-|Move |d=s |
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|MTPS s |1064SS|****|Move To Processor Status |PS=s (byte)|
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|MUL s,r |070RSS|**0*|Multiply |r=r*s (EIS)|
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|NEGb d |B054DD|****|Negate |d=-d |
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|NOP |000240|----|No Operation | |
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|RESET |000005|----|Reset external bus | |
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|RETURN |000207|----|Return from subroutine | (= RTS PC)|
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|ROLb d |B061DD|****|Rotate Left |d={C,d}<- |
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|RORb d |B060DD|****|Rotate Right |d=->{C,d} |
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|RTI |000002|----|Return from Interrupt |{PC,PS}=(SP)+|
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|RTS r |00020R|----|Return from Subroutine |PC=r,r=(SP)+ |
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|RTT |000006|----|Return from interrupt |Inhibit T-bit|
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|SBCb d |B056DD|****|Subtract Carry |d=d-C |
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|SCC |000277|1111|Set all Condition Codes |{C,N,V,Z}=1 |
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|SEC |000261|---1|Set Carry |C=1 |
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|SEN |000270|1---|Set Negative |N=1 |
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|SEV |000262|--1-|Set Overflow |V=1 |
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|SEZ |000264|-1--|Set Zero |Z=1 |
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|SOB r,a |077RNN|----|Subtract One and Branch |PC=PC-2*NN |
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|SUB s,d |16SSDD|****|Subtract |d=d-s |
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|SWAB d |0003DD|**00|Swap Bytes | |
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|SXT d |0067DD|-*0-|Sign Extend |d=0 or -1 |
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|TRAP t |1044TT|----|Trap |Vector at 34 |
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|TSTb d |B055DD|**00|Test |d |
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|WAIT |000001|----|Wait for interrupt | |
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|XOR r,d |074RDD|**0-|Exclusive OR |d=dxr |
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----------------------------------------------------------------
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----------------------------------------------------------------
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|Mnemonic |Opcode|NZVC|Description |
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|---------+------+----+----------------------------------------|
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| | B| |0 for word, 1 for byte (1 bit) |
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| | DD| |Destination field (6 bits) |
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| | N| |Number (3 bits) |
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| | NN| |Number (6 bits) |
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| | R| |Register (3 bits, R0-5/SP/PC) |
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| | SS| |Source field (6 bits) |
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| | TT| |Number (8 bits) |
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| | XX| |Offset (8 bits, -128 to +127) |
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|----------------+----+----------------------------------------|
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| PSW |-*01|Flag unaffected/affected/reset/set |
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| | |Priority interrupt (Bit 7) |
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| T | |Trace trap (Bit 4) |
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| N |N |Negative (Bit 3) |
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| Z | Z |Zero (Bit 2) |
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| V | V |Overflow (Bit 1) |
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| C | C|Carry (Bit 0) |
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|---------------------+----------------------------------------|
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| r |Register (mode 0) |
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| (r) |Register deferred (mode 1) |
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| @r | ditto |
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| (r)+ |Auto-increment (mode 2) |
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| @(r)+ |Auto-increment deferred (mode 3) |
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| -(r) |Auto-decrement (mode 4) |
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| @-(r) |Auto-decrement deferred (mode 5) |
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| nn(r) |Index (mode 6) |
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| @nn(r) |Index deferred (mode 7) |
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| #nn |Immediate (mode 2, r=PC) |
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| @#nn |Absolute (mode 3, r=PC) |
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| nn |Relative (mode 6, r=PC) |
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| @nn |Relative deferred (mode 7, r=PC) |
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|---------------------+----------------------------------------|
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| Rn |General purpose Register (16-bit, n=0-5)|
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| SP |Stack Pointer (16-bit, R6) |
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| PC |Program Counter (16-bit, R7) |
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| PS |Processor Status (16-bit) |
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|---------------------+----------------------------------------|
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| a |Relative address |
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| b |Blank or B for word or byte operand(s) |
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| d |Destination |
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| n |Register Number (0 to 5) |
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| nn |16-bit expression (0 to 65535) |
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| r |Register (Rn,SP,PC) |
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| s |Source |
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| t |Trap number |
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| + |Arithmetic addition |
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| - |Arithmetic subtraction |
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| * |Arithmetic multipication |
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| / |Arithmetic division |
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| ^ |Arithmetic exponent |
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| & |Logical AND |
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| ~ |Logical NOT |
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| v |Logical inclusive OR |
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| x |Logical exclusive OR |
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| <- |Rotate left |
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| -> |Rotate right |
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| { } |Combination of operands |
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|---------------------+----------------------------------------|
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| DEC |Digital Equipment Corporation |
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| EIS |Extended fixed point Instruction Set |
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| FIS |Floating point Instruction Set |
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| LSI |Large Scale Integration |
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| PSW |Processor Status Word |
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|---------------------+----------------------------------------|
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| 000 |Reserved vector |
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| 004 |Time-out/system error vector |
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| 010 |Illegal and reserved instruction vector |
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| 014 |BPT instruction vector |
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| 020 |IOT instruction vector |
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| 024 |Power fail vector |
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| 030 |EMT instruction vector |
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| 034 |TRAP instruction vector |
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| 060 |Console input device vector |
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| 064 |Console output device vector |
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| 100 |External event line interrupt vector |
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| 244 |FIS vector (optional) |
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| 160000-177776 |Device addresses |
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----------------------------------------------------------------
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