241 lines
15 KiB
Plaintext
241 lines
15 KiB
Plaintext
----------------------------------------------------------------
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| 88888 000 88888 5555555 A |
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| 8 8 0 0 8 8 5 A A |
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| 8 8 0 0 0 8 8 5 A A |
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| 88888 0 0 0 88888 555555 AAAAAAA |
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| 8 8 0 0 0 8 8 5 A A |
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| 8 8 0 0 8 8 5 A A |
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| 88888 000 88888 555555 A A |
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| 8085A MICROPROCESSOR Instruction Set Summary |
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| _________ _________ |
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| _| \__/ |_ |
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| --> X1 |_|1 40|_| Vcc (+5V) |
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| _| |_ |
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| --> X2 |_|2 39|_| HOLD <-- |
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| _| |_ |
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| <-- RESET OUT |_|3 38|_| HLDA --> |
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| _| |_ |
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| <-- SOD |_|4 37|_| CLK (OUT) --> |
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| _| |_ ________ |
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| --> SID |_|5 36|_| RESET IN <-- |
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| _| |_ |
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| --> TRAP |_|6 35|_| READY <-- |
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| _| |_ _ |
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| --> RST 7.5 |_|7 34|_| IO/M --> |
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| _| |_ |
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| --> RST 6.5 |_|8 33|_| S1 --> |
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| _| |_ __ |
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| --> RST 5.5 |_|9 32|_| RD --> |
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| _| |_ __ |
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| --> INTR |_|10 8085A 31|_| WR --> |
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| ____ _| |_ |
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| <-- INTA |_|11 30|_| ALE --> |
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| _| |_ |
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| <--> AD0 |_|12 29|_| S0 --> |
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| _| |_ |
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| <--> AD1 |_|13 28|_| A15 --> |
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| _| |_ |
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| <--> AD2 |_|14 27|_| A14 --> |
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| _| |_ |
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| <--> AD3 |_|15 26|_| A13 --> |
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| _| |_ |
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| <--> AD4 |_|16 25|_| A12 --> |
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| _| |_ |
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| <--> AD5 |_|17 24|_| A11 --> |
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| _| |_ |
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| <--> AD6 |_|18 23|_| A10 --> |
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| _| |_ |
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| <--> AD7 |_|19 22|_| A9 --> |
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| _| |_ |
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| Vss |_|20 21|_| A8 --> |
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| |______________________| |
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|Written by Jonathan Bowen |
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| Programming Research Group |
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| Oxford University Computing Laboratory |
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| 8-11 Keble Road |
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| Oxford OX1 3QD |
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| England |
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| Tel +44-865-273840 |
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|Created May 1983 |
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|Updated April 1985 |
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|Issue 1.1 Copyright (C) J.P.Bowen 1985|
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----------------------------------------------------------------
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----------------------------------------------------------------
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|Mnemonic |Op|SZAPC|~s|Description |Notes |
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|---------+--+-----+--+--------------------------+-------------|
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|ACI n |CE|*****| 7|Add with Carry Immediate |A=A+n+CY |
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|ADC r |8F|*****| 4|Add with Carry |A=A+r+CY(21X)|
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|ADC M |8E|*****| 7|Add with Carry to Memory |A=A+[HL]+CY |
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|ADD r |87|*****| 4|Add |A=A+r (20X)|
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|ADD M |86|*****| 7|Add to Memory |A=A+[HL] |
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|ADI n |C6|*****| 7|Add Immediate |A=A+n |
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|ANA r |A7|****0| 4|AND Accumulator |A=A&r (24X)|
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|ANA M |A6|****0| 7|AND Accumulator and Memory|A=A&[HL] |
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|ANI n |E6|**0*0| 7|AND Immediate |A=A&n |
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|CALL a |CD|-----|18|Call unconditional |-[SP]=PC,PC=a|
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|CC a |DC|-----| 9|Call on Carry |If CY=1(18~s)|
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|CM a |FC|-----| 9|Call on Minus |If S=1 (18~s)|
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|CMA |2F|-----| 4|Complement Accumulator |A=~A |
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|CMC |3F|----*| 4|Complement Carry |CY=~CY |
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|CMP r |BF|*****| 4|Compare |A-r (27X)|
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|CMP M |BF|*****| 7|Compare with Memory |A-[HL] |
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|CNC a |D4|-----| 9|Call on No Carry |If CY=0(18~s)|
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|CNZ a |C4|-----| 9|Call on No Zero |If Z=0 (18~s)|
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|CP a |F4|-----| 9|Call on Plus |If S=0 (18~s)|
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|CPE a |EC|-----| 9|Call on Parity Even |If P=1 (18~s)|
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|CPI n |FE|*****| 7|Compare Immediate |A-n |
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|CPO a |E4|-----| 9|Call on Parity Odd |If P=0 (18~s)|
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|CZ a |CC|-----| 9|Call on Zero |If Z=1 (18~s)|
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|DAA |27|*****| 4|Decimal Adjust Accumulator|A=BCD format |
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|DAD B |09|----*|10|Double Add BC to HL |HL=HL+BC |
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|DAD D |19|----*|10|Double Add DE to HL |HL=HL+DE |
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|DAD H |29|----*|10|Double Add HL to HL |HL=HL+HL |
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|DAD SP |39|----*|10|Double Add SP to HL |HL=HL+SP |
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|DCR r |3D|****-| 4|Decrement |r=r-1 (0X5)|
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|DCR M |35|****-|10|Decrement Memory |[HL]=[HL]-1 |
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|DCX B |0B|-----| 6|Decrement BC |BC=BC-1 |
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|DCX D |1B|-----| 6|Decrement DE |DE=DE-1 |
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|DCX H |2B|-----| 6|Decrement HL |HL=HL-1 |
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|DCX SP |3B|-----| 6|Decrement Stack Pointer |SP=SP-1 |
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|DI |F3|-----| 4|Disable Interrupts | |
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|EI |FB|-----| 4|Enable Interrupts | |
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|HLT |76|-----| 5|Halt | |
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|IN p |DB|-----|10|Input |A=[p] |
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|INR r |3C|****-| 4|Increment |r=r+1 (0X4)|
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|INR M |3C|****-|10|Increment Memory |[HL]=[HL]+1 |
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|INX B |03|-----| 6|Increment BC |BC=BC+1 |
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|INX D |13|-----| 6|Increment DE |DE=DE+1 |
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|INX H |23|-----| 6|Increment HL |HL=HL+1 |
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|INX SP |33|-----| 6|Increment Stack Pointer |SP=SP+1 |
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|JMP a |C3|-----| 7|Jump unconditional |PC=a |
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|JC a |DA|-----| 7|Jump on Carry |If CY=1(10~s)|
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|JM a |FA|-----| 7|Jump on Minus |If S=1 (10~s)|
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|JNC a |D2|-----| 7|Jump on No Carry |If CY=0(10~s)|
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|JNZ a |C2|-----| 7|Jump on No Zero |If Z=0 (10~s)|
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|JP a |F2|-----| 7|Jump on Plus |If S=0 (10~s)|
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|JPE a |EA|-----| 7|Jump on Parity Even |If P=1 (10~s)|
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|JPO a |E2|-----| 7|Jump on Parity Odd |If P=0 (10~s)|
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|JZ a |CA|-----| 7|Jump on Zero |If Z=1 (10~s)|
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|LDA a |3A|-----|13|Load Accumulator direct |A=[a] |
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|LDAX B |0A|-----| 7|Load Accumulator indirect |A=[BC] |
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|LDAX D |1A|-----| 7|Load Accumulator indirect |A=[DE] |
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|LHLD a |2A|-----|16|Load HL Direct |HL=[a] |
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|LXI B,nn |01|-----|10|Load Immediate BC |BC=nn |
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|LXI D,nn |11|-----|10|Load Immediate DE |DE=nn |
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|LXI H,nn |21|-----|10|Load Immediate HL |HL=nn |
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|LXI SP,nn|31|-----|10|Load Immediate Stack Ptr |SP=nn |
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|MOV r1,r2|7F|-----| 4|Move register to register |r1=r2 (1XX)|
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|MOV M,r |77|-----| 7|Move register to Memory |[HL]=r (16X)|
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|MOV r,M |7E|-----| 7|Move Memory to register |r=[HL] (1X6)|
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|MVI r,n |3E|-----| 7|Move Immediate |r=n (0X6)|
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|MVI M,n |36|-----|10|Move Immediate to Memory |[HL]=n |
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|NOP |00|-----| 4|No Operation | |
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|ORA r |B7|**0*0| 4|Inclusive OR Accumulator |A=Avr (26X)|
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|ORA M |B6|**0*0| 7|Inclusive OR Accumulator |A=Av[HL] |
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|ORI n |F6|**0*0| 7|Inclusive OR Immediate |A=Avn |
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|OUT p |D3|-----|10|Output |[p]=A |
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|PCHL |E9|-----| 6|Jump HL indirect |PC=[HL] |
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|POP B |C1|-----|10|Pop BC |BC=[SP]+ |
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|POP D |D1|-----|10|Pop DE |DE=[SP]+ |
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|POP H |E1|-----|10|Pop HL |HL=[SP]+ |
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|POP PSW |F1|-----|10|Pop Processor Status Word |{PSW,A}=[SP]+|
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----------------------------------------------------------------
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----------------------------------------------------------------
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|Mnemonic |Op|SZAPC|~s|Description |Notes |
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|---------+--+-----+--+--------------------------+-------------|
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|PUSH B |C5|-----|12|Push BC |-[SP]=BC |
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|PUSH D |D5|-----|12|Push DE |-[SP]=DE |
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|PUSH H |E5|-----|12|Push HL |-[SP]=HL |
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|PUSH PSW |F5|-----|12|Push Processor Status Word|-[SP]={PSW,A}|
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|RAL |17|----*| 4|Rotate Accumulator Left |A={CY,A}<- |
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|RAR |1F|----*| 4|Rotate Accumulator Righ |A=->{CY,A} |
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|RET |C9|-----|10|Return |PC=[SP]+ |
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|RC |D8|-----| 6|Return on Carry |If CY=1(12~s)|
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|RIM |20|-----| 4|Read Interrupt Mask |A=mask |
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|RM |F8|-----| 6|Return on Minus |If S=1 (12~s)|
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|RNC |D0|-----| 6|Return on No Carry |If CY=0(12~s)|
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|RNZ |C0|-----| 6|Return on No Zero |If Z=0 (12~s)|
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|RP |F0|-----| 6|Return on Plus |If S=0 (12~s)|
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|RPE |E8|-----| 6|Return on Parity Even |If P=1 (12~s)|
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|RPO |E0|-----| 6|Return on Parity Odd |If P=0 (12~s)|
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|RZ |C8|-----| 6|Return on Zero |If Z=1 (12~s)|
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|RLC |07|----*| 4|Rotate Left Circular |A=A<- |
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|RRC |0F|----*| 4|Rotate Right Circular |A=->A |
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|RST z |C7|-----|12|Restart (3X7)|-[SP]=PC,PC=z|
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|SBB r |9F|*****| 4|Subtract with Borrow |A=A-r-CY |
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|SBB M |9E|*****| 7|Subtract with Borrow |A=A-[HL]-CY |
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|SBI n |DE|*****| 7|Subtract with Borrow Immed|A=A-n-CY |
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|SHLD a |22|-----|16|Store HL Direct |[a]=HL |
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|SIM |30|-----| 4|Set Interrupt Mask |mask=A |
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|SPHL |F9|-----| 6|Move HL to SP |SP=HL |
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|STA a |32|-----|13|Store Accumulator |[a]=A |
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|STAX B |02|-----| 7|Store Accumulator indirect|[BC]=A |
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|STAX D |12|-----| 7|Store Accumulator indirect|[DE]=A |
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|STC |37|----1| 4|Set Carry |CY=1 |
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|SUB r |97|*****| 4|Subtract |A=A-r (22X)|
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|SUB M |96|*****| 7|Subtract Memory |A=A-[HL] |
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|SUI n |D6|*****| 7|Subtract Immediate |A=A-n |
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|XCHG |EB|-----| 4|Exchange HL with DE |HL<->DE |
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|XRA r |AF|**0*0| 4|Exclusive OR Accumulator |A=Axr (25X)|
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|XRA M |AE|**0*0| 7|Exclusive OR Accumulator |A=Ax[HL] |
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|XRI n |EE|**0*0| 7|Exclusive OR Immediate |A=Axn |
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|XTHL |E3|-----|16|Exchange stack Top with HL|[SP]<->HL |
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|------------+-----+--+----------------------------------------|
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| PSW |-*01 | |Flag unaffected/affected/reset/set |
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| S |S | |Sign (Bit 7) |
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| Z | Z | |Zero (Bit 6) |
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| AC | A | |Auxilary Carry (Bit 4) |
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| P | P | |Parity (Bit 2) |
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| CY | C| |Carry (Bit 0) |
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|---------------------+----------------------------------------|
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| a p |Direct addressing |
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| M z |Register indirect addressing |
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| n nn |Immediate addressing |
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| r |Register addressing |
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|---------------------+----------------------------------------|
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|DB n(,n) |Define Byte(s) |
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|DB 'string' |Define Byte ASCII character string |
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|DS nn |Define Storage Block |
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|DW nn(,nn) |Define Word(s) |
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|---------------------+----------------------------------------|
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| A B C D E H L |Registers (8-bit) |
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| BC DE HL |Register pairs (16-bit) |
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| PC |Program Counter register (16-bit) |
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| PSW |Processor Status Word (8-bit) |
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| SP |Stack Pointer register (16-bit) |
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|---------------------+----------------------------------------|
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| a nn |16-bit address/data (0 to 65535) |
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| n p |8-bit data/port (0 to 255) |
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| r |Register (X=B,C,D,E,H,L,M,A) |
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| z |Vector (X=0H,8H,10H,18H,20H,28H,30H,38H)|
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|---------------------+----------------------------------------|
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| + - |Arithmetic addition/subtraction |
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| & ~ |Logical AND/NOT |
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| v x |Logical inclusive/exclusive OR |
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| <- -> |Rotate left/right |
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| <-> |Exchange |
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| [ ] |Indirect addressing |
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| [ ]+ -[ ] |Indirect address auto-inc/decrement |
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| { } |Combination operands |
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| ( X ) |Octal op code where X is a 3-bit code |
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| If ( ~s) |Number of cycles if condition true |
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----------------------------------------------------------------
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