545 lines
24 KiB
Plaintext
545 lines
24 KiB
Plaintext
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OVERVIEW OF BELLCORE METROCORE\*(Tm NETWORK
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A. Albanese, M. W. Garrett, A. Ippoliti,
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M. A. Karr, M. Maszczak, and D. Shia
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Bell Communications Research
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Morristown, New Jersey 07960, USA
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(201) 829-4291
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The Bellcore METROCORE\*(Tm network is a test bed prototype of a
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metropolitan area network (MAN) for exploring new network concepts
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and technology applications in broadband communications.
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The present design and status of the METROCORE network
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research prototype are outlined.
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This system operates at 150 Mb/s with the potential for
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upgrading to 2.4 Gb/s.
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A basic hardware architecture has been designed which consists
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of a network interface (media access control (MAC) layer), and
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several independent, modular units that interface to various services.
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At the MAC layer, integrated services are supported by giving priority to
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those traffic types requiring bounded delay.
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The organization is modular, allowing components and services to be added
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or improved while redesigning the minimum amount of hardware.
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The software network architecture has also been designed and it includes
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a network controller to configure, monitor, and administer the network.
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The Bellcore METROCORE\*(Tm
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METROCORE is a trademark of Bell Communications Research, Inc.
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This paper will be presented at the IFIP WG 6.4 Workshop HSLAN'88,
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April 14-15, 1988, Liege, Belgium.
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network is a Metropolitan Area Network (MAN)
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prototype using an enhanced version of Fasnet [LIMB82]
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as its Media Access Control (MAC) protocol.
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This prototype
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serves as a test-bed for research in the integration of
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diverse services onto a unified packet switched network.
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The protocol provides special access for traffic with
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delay constraints.
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There is also a mechanism for ensuring
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fairness among the active nodes.
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Nodes are connected to each other by a dual bus network
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similar to the architecture being considered by IEEE 802.6.
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Rather than using passive taps as in the original Fasnet proposal,
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active regeneration is used with optical fault bypass devices
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and a stand by fiber optic link to insure fail-safty (Figure^1).
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"Metrocore implementation with four nodes."
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The hardware designed for each node includes a
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MAC layer circuit which interfaces the node to the
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network.
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This exchanges packets across a specialized internal
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communication bus with a variety of "service processors," (SPs)
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which serve as interfaces to the services running on the network.
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The internal bus is called the "Fast Packet Bus" (FPB), and
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is implemented in a similar way to the backplane of a double VME card cage.
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However, only the physical VME specification is used since
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the VME electrical definition,
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like most computer backplanes,
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can not provide as much bandwidth as we desire for this application.
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Each SP ideally occupies one board, allowing several services
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to be present in a node.
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In addition to the MAC circuit and the SPs, there
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is a node controller circuit which keeps track of statistics
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for billing, management, administration, and operations and takes care
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of diagnostics and fault control.
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The service processors we anticipate include services such as
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telephone, television, computers, disk servers, and a LAN interconnection.
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The LAN service processor was designed first since
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it is an important service to explore in the near term,
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and because this allows us to connect (indirectly) anything that
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already uses Ethernet.
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This processor consists of five modular circuits implemented in
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four boards that may be modified for use in other SPs.
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This processor implements a transparent
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protocol which encapsulates Ethernet packets for transport
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across Fasnet and retransmission on a remote Ethernet.
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Other suggested protocols for service integration for interconnected
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LANs [FRAT87] and routing for interconnected MANs [STRG87a,b]
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have not been implemented yet.
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Figure^2 shows the system block diagram. Each component is described
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below, followed by brief discussions of the software architecture,
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and a Gb/s network enhancement.
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"Metrocore node."
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"Optical Transmission System"
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We are presently using an off-the-shelf transmission system
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with single mode optical fibers at 150 Mb/s and
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a wavelength of 1.3 &mu m&.
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This system was chosen because it provides a virtual clear channel,
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and can tolerate the long strings of consecutive zeros which occur between
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the head-end node (which sends blank packets) and the node that uses
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a packet by filling in the empty data field.
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The system does its own scrambling and clock recovery.
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Connections between nodes are point-to-point, but
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an optical fail-safe devices may be inserted to make the node appear
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transparent in case of a local node failure [ALBA82, LOH86].
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A stand by fiber optical link allows network reconfiguration in case one of
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the links is not functioning.
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"MAC Chip"
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This chip is the major component of the MAC circuit.
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The MAC chip executes the media access layer protocol and thus governs the
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flow of data onto the network.
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Two chips are needed for the two directions of traffic on the network.
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The design is implemented as a
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semi-custom chip manufactured by Motorola, using emitter coupled logic
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(ECL) technology for high-speed performance.
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The maximum speed was measured at 310^Mb/s.
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The MAC chip replaces a whole board of SSI/MSI chips in a
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previous prototype.
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The MAC chip reads the various fields of the packet header to
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execute proper transmission, and signals interface circuits
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for reception of packets.
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Other functions include synchronization of the chip to the incoming packet
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stream, generation of timing signals and 1 ×& 16 serial to parallel
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conversion.
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Each chip contains the circuitry needed to execute special
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functions associated with the end nodes.
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Thus, as a fail-safe mechanism,
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a middle node may become the head-end if the original head-end fails or
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if the network becomes severed.
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The chip was designed and simulated on a Daisy CAD workstation using
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a library of components made available from Motorola.
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The Motorola
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computer system was then used for the final timing simulation, race-condition
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test, placement and routing of the metal paths.
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This chip is equivalent to 2500 ECL gates and comes in a 149-pin PGA
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package. 98% of the available circuitry and pins were used.
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"MAC Circuit"
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The MAC circuit consists of MAC chips, address recognition circuits
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(address filters) , bus arbiters, a head-end enable detection circuit
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(activity detect), a head-end access field generator,
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ECL/TTL converters, control circuitry, and a power-up reset
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circuit (see Figure^3).
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There is generally two of everything due to the two unidirectional
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busses used in Fasnet.
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"Medium Access Control Circuit."
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Each MAC chip feeds incoming data, in a 16-bit parallel word, into an
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address recognition circuit which compares the address field
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of the packet to a group address and a single node address.
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Thus a node may be addressed individually or as part of a multi-cast group.
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The link-layer address is structured so that the first bit (most
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significant) indicates group or node address (0/1), the next
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11 bits identify the node or group, and the last four constitute
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a sub-address indicating the intended service processor.
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The address circuit is implemented
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in TTL logic with ECL/TTL converters between the MAC chip and itself.
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Data and control information is passed on to the service processors
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through the two outgoing paths to the Fast Packet Bus.
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Four bus arbiter circuits are included for the four incoming paths
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from the FPB.
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These paths carry data destined for transmission
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from the service processors to the MAC chips.
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There are "data" and "voice" paths for each of two MAC chips.
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(The data and voice paths are not limited to those services but are used
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to differentiate between traffic which can tolerate network delays (low
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priority) and those which can not (high priority).
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The paths are separated
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because the two Fasnet lines operate independently, and the two cycles
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(for different priority traffic) are also independent.
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The bus arbiters choose which of competing service processors gets
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next access to a given path of the FPB, and therefore to the network.
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The choice is made using a simple round-robin scheme.
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Processors using the same FBP path
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are not further prioritized, although this could be done
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using a more complex bus arbiter circuit.
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An activity detection circuit monitors the
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synchronization at the receiver to discover whether
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the node is to be head-end or not.
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The head-end node will
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have a desable receiver for the line that it heads and thus
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would always remain head-end.
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A middle node (Figure^1) will become
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head-end in the event of a failure just upstream of itself.
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If the receiver does not provide a carrier detect signal,
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the MAC synchronization function could be used:
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When the MAC fails to synchronize for 2 msec (for example),
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it turns on its head-end function, and then monitors the incoming
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data stream for a valid Fasnet synchronization pattern.
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Reception of such a pattern would then turn off the head-end
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function for that node returning to its middle node function.
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The access field generator circuit (see Figure^3), implemented as
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a PLA (programmable logic array) is required if a node is a head-end.
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This takes care of "turning around" the start and end bits of the Fasnet
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access field, which in turn operate the network cycles.
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Every
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node which might be head-end must have this.
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It is possible
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to avoid putting this circuit in every node; the tradeoff being
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that all nodes between the fault and the first head-end-capable
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node would go down.
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The MAC chips require information to determine system parameters such
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as packet size etc.
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These, as well as the node addresses are stored
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in a small register and are generally programmed on power-up by a control
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circuit in the node.
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The remaining functions in Figure^3 are the power-up reset circuit
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which holds reset high until the power supply voltage stablizes;
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and a local oscillator which serves as system clock in head-end nodes.
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"Fast Packet Bus"
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The backplane of the card cage has two 96-pin connectors which carry
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the two incoming paths to the processors, and the four outgoing paths
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to the MAC circuit.
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Several pins also supply power and ground (TTL) to the boards.
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In addition, there is a synchronous serial line which allows the
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node controller SP to down load and read the stored MAC parameters.
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On each incoming path, there are 16 bits of data; a four bit sub-address
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which identifies the processor to receive the packet; a four bit control
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field which comes from the beginning of the information part of the
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packet, and may be used optionally to give the SP a code already parsed
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from the packet. A signal called
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"Packet Ready" indicates the beginning of a new, valid packet, and
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two clock signals (at about 10 MHz and 20 MHz) are given from which
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the MAC circuit's two phase clock (&phi&1 and &phi&2) are derived.
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On each outgoing path there are again, 16 bits of data.
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A strobe
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signal from the MAC chip prompts each word from the processor.
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Each processor (up to four) has its own set of handshaking lines with
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the bus arbiter.
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If more than four processors use a single path, then this handshaking
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may be daisy-chained on every fourth processor.
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The processor wishing to
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transmit raises its "request" line; the bus arbiter selects the next
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requesting processor in turn and responds with an "acknowledge."
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The processor
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then raises its first word of data together with
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"data ready."
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When the MAC gets access to the network, it will strobe the processor
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for the following words.
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This type of internal node bus uses a lot of pins (192).
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The choice could be made to reduce the number of wires by time multiplexing
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signals of the various buses.
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This however, would require a large and
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complex buffer on the MAC circuit, which would be more difficult
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than having a large backplane bus.
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The present FPB has the advantage
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of not presenting any bottleneck at all beyond that caused by
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the node access to the network (i. e. same-priority, same-direction packets
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must compete for the network at the MAC chip anyway).
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"Node Controller Circuit"
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When a node is powered up, all processors as well as the
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MAC circuit must know the node's address.
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This circuit is responsible for
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providing this information as well as certain MAC chip parameters.
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This circuit would also monitor
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statistics about the node's activities for billing etc.
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There may
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be a central control node for the whole network with which this circuit would
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communicate to reconfigure addresses, diagnose network failures or exchange
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statistical information.
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The controller circuit would
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therefore be able to construct Fasnet packets and transmit and receive
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like any other service processor.
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All the functions of the node controller were implemented in software that run
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in the 68000 of the Ethernet Circuit in the LAN processor (see Figure^4).
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"LAN Service Processor"
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This processor does the function of a LAN/MAN bridge (see Figure^4),
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it carries packets transparently between
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two Ethernet LANs which may be separated by considerable distance.
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A description of the functionality and philosophy of design
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may be found in [ALBA86, DEGR86].
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The LAN service processor consists of five circuits implemented on four boards,
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which could probably be integrated down to one board using a VLSI technology
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like that used for the MAC chip.
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Each circuit performs a special task:
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(1) Input Buffer, (2) Output Buffer,
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(3) Depacketizer, (4) Packetizer, and (5) the Ethernet Circuit
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and Node Controller.
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These are general building blocks for any service processor.
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The buffers are rather large, since a LAN is expected to generate more
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traffic than a computer interface would, for example, but the design
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can be scaled down and used in any case.
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The packetizer and depacketizer
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are bit-sliced processors offering very high throughput for communications,
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but weak processing power.
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The Ethernet circuit is a specialized processor
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with potential for complex processing.
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It can be tailored for another
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purpose by substituting another interface for the Ethernet dependent
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parts.
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This processor is not, however, suited as a general purpose
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computer because of the limited memory configuration.
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Rather, it should be seen as a powerful dedicated controller.
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"LAN Service Processor and Node Controller."
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.H 2 "Input and Output Buffer Circuits"
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The input buffer connects to the incoming paths of the FPB.
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Each of the two large
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circular buffers are synchronized to their respective MAC clocks.
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Read
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and write pointers are generated for each buffer, and the circuit
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monitors whether the buffers are full or empty by
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comparing the values of the two pointers.
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The buffers themselves are
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16K ×& 16 RAM chips with very fast (35 nsec) access times.
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In this circuit, the 2-phase clock from the FPB is decoded and used.
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On the other side, the buffers feed the depacketizer circuit, which uses
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the clock of whichever input buffer it is reading at the time.
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Two finite state machines (PLAs) which are referred to as the
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"producer" and "consumer," govern the flow of data into
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and out of the buffer, respectively.
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The output buffer takes data from the packetizer circuit and stores it for
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transmission on the outgoing FPB.
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Many packets may be stored in
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the single buffer along with information about which outgoing path(s)
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each one is to be transmitted on.
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Packets destined for both directions
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on the network must be transmitted on each direction separately, since
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the two MAC chips
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cannot possibly be synchronized.
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"Depacketizer and Packetizer Circuits"
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The depacketizer and packetizer circuits are almost identical in hardware
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but different in software.
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The processor consists of an AMD
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2910 bit-sliced sequencer and an AMD 2116 ALU chip.
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The function performed
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involves stripping Fasnet headers from incoming packets and storing the
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Ethernet fragments away in a DRAM on the Ethernet Processor circuit, and
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then indicating to that circuit when a packet is completely reconstituted
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and ready for retransmission on Ethernet.
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The depacketizer circuit also contains an Ethernet address filter, which
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now consists of a hashing algorithm, but would ideally be implemented
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as a Content Addressable Memory (CAM), which may
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be available in the future.
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Ethernet packets are filtered so that only the ones intended for local
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Ethernet nodes are retransmitted.
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Others are dropped.
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The packetizer is the same processor as used in the depacketizer circuit,
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except that the task here is to transform whole Ethernet packets into
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bursts of Fasnet packets.
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The Ethernet packets are completely and
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transparently encapsulated.
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Addresses are not converted. Headers are
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added indicating Fasnet addresses and control information.
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An Ethernet
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address filter lets only those packets not destined for local Ethernet
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nodes to escape to the MAN.
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"Ethernet Processor Circuit"
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This circuit consists mainly of two dynamic RAM controller chips, with their
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respective banks of DRAM, which interface to the packetizer and depacketizer
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circuits;
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an AMD Local Area Network Controller for Ethernet (LANCE) chip; and
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a 68000 microprocessor chip.
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The 68000 takes care of initialization and
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memory management, and the LANCE, which is itself a dedicated
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microprocessor, takes care of getting traffic onto and
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off of the Ethernet.
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In addition, there are two UARTs on the 68000 which
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allow a terminal and a modem to be connected to the node
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for diagnostic purposes.
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"Network Software Architecture"
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For network management and operation purposes each network node
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is structured according to the Open System Interconnection (OSI)
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Reference Model to support communications between all the
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nodes and the network controller.
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Figure^5 shows the software network architecture.
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The Management Control Unit consists of network management
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and node management units.
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.FG "Network Software Architecture."
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The Network Management unit monitors the status of the network, collects
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statistical data from each node and stores it on a disk, provides hard
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copies of network statistics, and handles network set-up
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and configurations of the Ethernet LAN interconnections via a human
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administrator.
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The Node Management Unit performs self-test on power up and upon receiving
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requests from the Network Management Unit.
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It also provides remote reset and
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download capabilities to facilitate software updates and maintenances.
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It maintains configuration data and collects statistical data about local
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operations.
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Upon receiving requests from the Network Management Unit,
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it reports the most recent information about the node operations.
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It also monitors any fault events on the node.
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When a fault happens,
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it attempts to either correct the fault problem or to collect more information.
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In any case the fault is reported to the Network Management Unit along with
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the result of attempted recovery.
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In order to communicate reliably to each other, the Network Management Unit
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and the Node Management Unit require the Transport layer services.
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The Transport layer uses the Data Link layer services to handle
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connection setup and termination, flow control,
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multiplexing, fragmentation, and error detections and corrections.
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The Data Link layer deals with sending and receiving packets to and from
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other nodes without bit pattern errors.
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Please note that these reliable
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services are provided only for the management purposes.
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They do not interfere with transparent wiring services offered
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by the LAN processor.
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In another word, these protocols
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are logically separated from the transparent wiring services.
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"Multi-Gigabit/second MAC Circuit"
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This work investigates how to share the multigigabit/second
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transport capabilities offered by lightwave systems among a multitude
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of users and how to integrate the many broadband and narrowband services
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that a user may require.
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We have demonstrated a 1.2 Gb/s system to provide packet
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communications in the distributed switching system shown in Figure^6.
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The system provides multiple access at 1.2 Gb/s and consists
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of a unique node architecture that combines available
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lightwave, gallium arsenide, and silicon technologies [KARR87].
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"Gigabit/second access interface."
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Gallium arsenide (GaAs) multiplexer and demultiplexer ICs represent
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today's most advanced technology.
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Silicon very large scale integrated (VLSI) circuits have up to 100,000
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transistors on a chip,
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but generally do not operate in the Gb/s range.
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Commercially available GaAs ICs will work above 1 Gb/s
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and their circuit densities are rapidly advancing.
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We use 8:1/1:8 multiplexer/demultiplexer GaAs ICs made by
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Gigabit Logic Inc., together
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with our silicon MAC IC to divide the 1.2 Gb/s bandwidth into
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8 channels of 150 Mb/s.
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These devices are considered "medium-scale integration" (MSI)
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and contain about 200 gates.
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The data is controlled by a packet switching protocol using control fields
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only on one of the channels [GARR86].
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The protocol, based on Fasnet, is executed by the Media Access Control (MAC)
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chip.
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Other channels carry only data and are synchronized to the control channel.
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Thus each user has access to the full 1.2 Gb/s capacity on a per-packet basis.
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Some gallium arsenide integrated circuit components are becoming available
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in the 2 Gb/s range.
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A 16:1 multiplexer and a 1:16 demultiplexer operating at 2.4 Gb/s were built
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which could
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upgrade the 150 Mb/s MAC circuit to 2.4 Gb/s.
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Metropolitan area network technology enables users currently
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connected to local area networks, geographically limited
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within one building or office complex,
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to extend their range of networking interconnectivity.
|
||
Large corporations that have several LANs operational at separate sites
|
||
interspersed within an urban area will be able to utilize their resources
|
||
more effectively and make them more widely available through the use of
|
||
MAN networking.
|
||
|
||
The technology is demonstrated in a laboratory test bed.
|
||
Working prototypes demonstrate that present technology is capable to
|
||
interconnect 10 Mb/s LANs over MANs implemented at 150 Mb/s
|
||
and to be upgraded to 1.2 Gb/s in the near future.
|
||
|
||
"REFERENCES"
|
||
|
||
|
||
[ALBA82]
|
||
A. Albanese,
|
||
"Fail-Safe Nodes for Lightguide Digital Networks,"
|
||
Bell System Technical Journal, Vol 61, Nr 2, pp 247-256, February 1982.
|
||
[ALBA86]
|
||
A. Albanese, G. DeGrandi, M.W. Garrett, "An Architecture for
|
||
Transparent MAN/LAN Gateways," IEEE International Conference on
|
||
Communications, Toronto, Canada, June 1986.
|
||
[DEGR86]
|
||
G. DeGrandi, M.W. Garrett, A. Albanese, T.H. Lee, "The Design and
|
||
Implementation of a Transparent MAN/LAN Gateway," Proc.
|
||
EFOC/LAN'86, Information Gatekeepers Inc., Amsterdam June 1986.
|
||
[FRAT87]
|
||
L. Fratta and A. Albanese,
|
||
"Service Integration for Interconnected LANs,"
|
||
The Third International Conference on Data Communication Systems and Their
|
||
Performance, Rio de Janeiro, Brazil, June 22, 1987.
|
||
[GARR86]
|
||
M.W. Garrett, J.O. Limb, A. Albanese, "Multiple Gb/s Fiber-Optic
|
||
Metropolitan Area Network," IEEE International Conference on
|
||
Communications, Toronto, Canada, June 1986.
|
||
[KARR87]
|
||
M. Karr, A. Albanese, M. Garrett, K.W. Loh, M. Maszczak,
|
||
"Experimental Gigabit Packet Communications Network,"
|
||
IEEE Optical Fiber Communications Conference,
|
||
Reno NV, February 1987.
|
||
[LIMB82]
|
||
J.O. Limb, C. Flores, "Description of Fasnet - A
|
||
Unidirectional Local Area Communications Network," Bell
|
||
Syst Tech Journal Vol 61, No 7, p 1413, Sept 1982.
|
||
[LOH86]
|
||
K. W. Loh, M. Karr, A. Albanese, W. C. Young, L. Curtis,
|
||
J. Baran, and L. McCaughan,
|
||
"Fail-Safe Nodes for Fiber Networks,"
|
||
Optical Fiber Conference, Atlanta, Georgia, February 24-26, 1986.
|
||
[STR87a]
|
||
L. Strigini, L. Fratta, and A. Albanese,
|
||
"Multicast Services on High-Speed Interconnected LANs,"
|
||
1987 Workshop on High Speed LANs,
|
||
Aachen, West Germany,
|
||
February 16-17, 1987.
|
||
[STR87b]
|
||
L. Strigini, L. Fratta, and A. Albanese,
|
||
"Explicit Offset Routing for Interconnecting High-Speed Networks,"
|
||
EFOC/LAN 87,
|
||
Basel Switzerland,
|
||
June 3-5, 1987.
|
||
|