507 lines
14 KiB
Plaintext
507 lines
14 KiB
Plaintext
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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INTRO TO DMA by Draeden of VLA
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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DMA means Direct Memory Access. You probably already know where and
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why you use it, so I'll skip right down to the dirty stuff. This all
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should speak for it's self, so... Enjoy.
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Draeden /VLA
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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To do a DMA transfer, you need to know a few things:
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1) Address of the memory to access
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2) Length of data to read/write
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This can all be put into a structure:
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STRUC DMAInfo
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Page db ?
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Offset dw ?
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Length dw ?
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ENDS
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Page is the highest 4 bits of the absolute 20 bit address of the memory
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location. Note that DMA transfers CANNOT cross 64k page boundries.
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The Length is actually LENGTH-1; sending in a 0 will move 1 byte,
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sending a 0FFFFh will move 64k.
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<20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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; IN: DX:AX = segment/offset address of memory area
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;
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;OUT: DH = Page (0-F) (DL is destroyed)
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; AX = Offset
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<20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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PROC MakePage
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push bx
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mov bl,dh
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shr bl,4 ;isolate upper 4 bits of segment
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shl dx,4 ;make segment into ABS address
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add ax,dx ;add the offset and put it in AX
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adc bl,0 ;complete the addition
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mov dh,bl ;put the PAGE where it goes
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pop bx ; DH:AX is now the PAGE:OFFSET address
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ret
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ENDP
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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Programming DMA channels 0 thru 3
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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There are 3 ports that are DMA channel specific:
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1) The Page register
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2) The DMA count (length) register
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3) The memory address (offset register)
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They are as follows:
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DMACH PAGE ADDRESS LENGTH
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0 87h 0 1
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1 83h 2 3
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2 81h 4 5
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3 82h 6 7
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And now some general registers:
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DMA Mask Register: 0Ah
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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bit 7 - 3 = 0 Reserved
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bit 2 = 0 clear mask
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= 1 set mask
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bits 1 - 0 = 00 Select channel 0
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= 01 select channel 1
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= 10 select channel 2
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= 11 select channel 3
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USE: You must set the mask of the channel before you
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can reprogram it.
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DMA Mode Register: 0Bh
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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bit 7 - 6 = 00 Demand mode
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= 01 Signal mode
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= 10 Block mode
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= 11 Cascade mode
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bit 5 - 4 = 0 Reserved
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bit 3 - 2 = 00 Verify operation
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= 01 Write operation
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= 10 Read operation
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= 11 Reserved
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bits 1 - 0 = 00 Select channel 0
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= 01 select channel 1
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= 10 select channel 2
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= 11 select channel 3
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USE: Tell the DMAC what to do. Common modes are:
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48h (Read operation, Signal mode)
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Used to read data from host memory and send to whomever
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polls it.
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44h (Write operation, Signal mode)
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Used to write data taken from a device to memory.
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DMA clear byte ptr: 0Ch
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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USE: Send a zero to reset the internal ptrs
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WHAT TO DO:
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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1) Set the Mask bit for the channel
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mov al,4
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add al,[DMA_Channel]
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out 0ah,al
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2) Clear Byte Ptr
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sub al,al
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out 0Ch,al
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3) Set the DMA transfer mode
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mov al,48h ;MODE output (read)
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add al,[DMA_Channel]
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out 0Bh,al
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4) Set the memory ADDRESS and LENGTH
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; AX = offset
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; CX = Length
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;[DMA_Base] = port # of memory address
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mov dx,[DMA_Base]
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out dx,al ;send lower byte address
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mov al,ah
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out dx,al ;send high byte address
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inc dl ;point to Count port
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mov al,cl
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out dx,al ;send low byte length
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mov al,ch
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out dx,al ;send high byte length
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5) Set the DMA page
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; AL = Page
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mov dx,[Dma_Page]
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out dx,al ; write the Page
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6) Clear DMA mask bit
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mov al,[byte DMA_Channel]
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out 0Ah,al ; port 0Ah, DMA-1 mask reg bit
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7) Program the other device that is going to use the DMA output/input
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<20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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; This routine programs the DMAC for channels 0-3
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;
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; IN: [DMA_Channel], [DMAbaseAdd], [DMApageReg] must be setup
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; [DAMBaseAdd] = Memory Address port
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;
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; dh = mode
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; ax = address
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; cx = length
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; dl = page
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<20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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PROC Prog_DMA03 NEAR
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push bx
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mov bx,ax
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mov al,4
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add al,[DMA_Channel]
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out 0Ah,al ; mask reg bit
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sub al,al
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out 0Ch,al ; clr byte ptr
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mov al,dh
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add al,[DMA_Channel]
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out 0Bh,al ; set mode reg
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push dx
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mov dx,[DMAbaseAdd]
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mov al,bl
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out dx,al ; set base address low
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mov al,bh
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out dx,al ; set base address high
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inc dx ;point to length
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mov al,cl
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out dx,al ; set length low
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mov al,ch
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out dx,al ; set length high
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pop dx
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mov al,dl
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mov dx,[DmaPageReg]
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out dx,al ; set DMA page reg
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mov al,[DMA_Channel]
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out 0Ah,al ; unmask (activate) dma channel
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pop bx
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ret
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ENDP
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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Programming DMA channels 4 thru 7
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
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Again, there are 3 ports that are DMA channel specific:
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1) The Page register
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2) The DMA count (length) register
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3) The memory address (offset register
|
|||
|
|
|||
|
They are as follows:
|
|||
|
|
|||
|
DMACH PAGE ADDRESS LENGTH
|
|||
|
|
|||
|
4 8Fh C0h C2h
|
|||
|
|
|||
|
5 8Bh C4h C6h
|
|||
|
|
|||
|
6 89h C8h CAh
|
|||
|
|
|||
|
7 8Ah CCh CEh
|
|||
|
|
|||
|
|
|||
|
And now some general registers:
|
|||
|
|
|||
|
DMA Mask Register: 0D4h
|
|||
|
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
bit 7 - 3 = 0 Reserved
|
|||
|
|
|||
|
bit 2 = 0 clear mask
|
|||
|
= 1 set mask
|
|||
|
|
|||
|
bits 1 - 0 = 00 Select channel 4
|
|||
|
= 01 select channel 5
|
|||
|
= 10 select channel 6
|
|||
|
= 11 select channel 7
|
|||
|
|
|||
|
USE: You must set the mask of the channel before you
|
|||
|
can reprogram it.
|
|||
|
|
|||
|
DMA Mode Register: 0D6h
|
|||
|
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
bit 7 - 6 = 00 Demand mode
|
|||
|
= 01 Signal mode
|
|||
|
= 10 Block mode
|
|||
|
= 11 Cascade mode
|
|||
|
|
|||
|
bit 5 - 4 = 0 Reserved
|
|||
|
|
|||
|
bit 3 - 2 = 00 Verify operation
|
|||
|
= 01 Write operation
|
|||
|
= 10 Read operation
|
|||
|
= 11 Reserved
|
|||
|
|
|||
|
bits 1 - 0 = 00 Select channel 4
|
|||
|
= 01 select channel 5
|
|||
|
= 10 select channel 6
|
|||
|
= 11 select channel 7
|
|||
|
|
|||
|
USE: Tell the DMAC what to do. Common modes are:
|
|||
|
|
|||
|
48h (Read operation, Signal mode)
|
|||
|
Used to read data from host memory and send to whomever
|
|||
|
polls it.
|
|||
|
|
|||
|
44h (Write operation, Signal mode)
|
|||
|
Used to write data taken from a device to memory.
|
|||
|
|
|||
|
DMA clear byte ptr: 0D8h
|
|||
|
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
USE: Send a zero to reset the internal ptrs
|
|||
|
|
|||
|
|
|||
|
WHAT TO DO: (exactly the same thing, just different io PORTs)
|
|||
|
<EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
|
|||
|
1) Set the Mask bit for the channel
|
|||
|
|
|||
|
mov al,[DMA_Channel] ;because the DMA's are 4-7, bit #3
|
|||
|
out 0D4h,al ; is already set
|
|||
|
|
|||
|
2) Clear Byte Ptr
|
|||
|
|
|||
|
sub al,al
|
|||
|
out 0D8h,al
|
|||
|
|
|||
|
3) Set the DMA transfer mode
|
|||
|
|
|||
|
mov al,[DMA_Channel]
|
|||
|
sub al,4
|
|||
|
or al,48h ;MODE output (read)
|
|||
|
out 0D6h,al
|
|||
|
|
|||
|
4) Set the memory ADDRESS and LENGTH
|
|||
|
|
|||
|
; AX = offset
|
|||
|
; CX = Length
|
|||
|
;[DMA_Base] = port # of memory address
|
|||
|
|
|||
|
mov dx,[DMA_Base]
|
|||
|
out dx,al ;send lower byte address
|
|||
|
mov al,ah
|
|||
|
out dx,al ;send high byte address
|
|||
|
|
|||
|
add dl,2 ;point to Count port (seperated by 2)
|
|||
|
mov al,cl
|
|||
|
out dx,al ;send low byte length
|
|||
|
mov al,ch
|
|||
|
out dx,al ;send high byte length
|
|||
|
|
|||
|
5) Set the DMA page
|
|||
|
|
|||
|
; AL = Page
|
|||
|
|
|||
|
mov dx,[Dma_Page]
|
|||
|
out dx,al ; write the Page
|
|||
|
|
|||
|
6) Clear DMA mask bit
|
|||
|
|
|||
|
mov al,[byte DMA_Channel]
|
|||
|
and al,00000011b
|
|||
|
out 0d4h,al ; port 0Ah, DMA-1 mask reg bit
|
|||
|
|
|||
|
7) Program the other device that is going to use the DMA output/input
|
|||
|
|
|||
|
|
|||
|
<20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
; This routine programs the DMAC for channels 4-7
|
|||
|
;
|
|||
|
; IN: [DMA_Channel], [DMAbaseAdd], [DMApageReg] must be setup
|
|||
|
; [DAMBaseAdd] = Memory Address port
|
|||
|
;
|
|||
|
; dh = mode
|
|||
|
; ax = address
|
|||
|
; cx = length
|
|||
|
; dl = page
|
|||
|
<20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
PROC Prog_DMA47 NEAR
|
|||
|
push bx
|
|||
|
mov bx,ax
|
|||
|
|
|||
|
mov al,[DMA_Channel]
|
|||
|
out 0D4h,al ; mask reg bit
|
|||
|
|
|||
|
sub al,al
|
|||
|
out 0D8h,al ; clr byte ptr
|
|||
|
|
|||
|
mov al,[DMA_Channel]
|
|||
|
sub al,4
|
|||
|
add al,dh
|
|||
|
out 0D6h,al ; set mode reg
|
|||
|
|
|||
|
push dx
|
|||
|
|
|||
|
mov dx,[DMAbaseAdd]
|
|||
|
mov al,bl
|
|||
|
out dx,al ; set base address low
|
|||
|
mov al,bh
|
|||
|
out dx,al ; set base address high
|
|||
|
|
|||
|
add dl,2 ;point to length
|
|||
|
mov al,cl
|
|||
|
out dx,al ; set length low
|
|||
|
mov al,ch
|
|||
|
out dx,al ; set length high
|
|||
|
|
|||
|
pop dx
|
|||
|
|
|||
|
mov al,dl
|
|||
|
mov dx,[DmaPageReg]
|
|||
|
out dx,al ; set DMA page reg
|
|||
|
|
|||
|
mov al,[DMA_Channel]
|
|||
|
and al,00000011b
|
|||
|
out 0D4h,al ; unmask (activate) dma channel
|
|||
|
pop bx
|
|||
|
ret
|
|||
|
ENDP
|
|||
|
|
|||
|
<20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
; This routine programs the DMAC for channels 0-7
|
|||
|
;
|
|||
|
; IN: [DMA_Channel], [DMAbaseAdd], [DMApageReg] must be setup
|
|||
|
; [DAMBaseAdd] = Memory Address port
|
|||
|
;
|
|||
|
; dh = mode
|
|||
|
; ax = address
|
|||
|
; cx = length
|
|||
|
; dl = page
|
|||
|
<20><><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD><EFBFBD>
|
|||
|
PROC Prog_DMA NEAR
|
|||
|
push bx
|
|||
|
mov bx,ax
|
|||
|
|
|||
|
cmp [DMA_Channel],4
|
|||
|
jb @@DoDMA03
|
|||
|
|
|||
|
mov al,[DMA_Channel]
|
|||
|
out 0D4h,al ; mask reg bit
|
|||
|
|
|||
|
sub al,al
|
|||
|
out 0D8h,al ; clr byte ptr
|
|||
|
|
|||
|
mov al,[DMA_Channel]
|
|||
|
sub al,4
|
|||
|
add al,dh
|
|||
|
out 0D6h,al ; set mode reg
|
|||
|
|
|||
|
push dx
|
|||
|
|
|||
|
mov dx,[DMAbaseAdd]
|
|||
|
mov al,bl
|
|||
|
out dx,al ; set base address low
|
|||
|
mov al,bh
|
|||
|
out dx,al ; set base address high
|
|||
|
|
|||
|
add dl,2 ;point to length
|
|||
|
mov al,cl
|
|||
|
out dx,al ; set length low
|
|||
|
mov al,ch
|
|||
|
out dx,al ; set length high
|
|||
|
|
|||
|
pop dx
|
|||
|
|
|||
|
mov al,dl
|
|||
|
mov dx,[DmaPageReg]
|
|||
|
out dx,al ; set DMA page reg
|
|||
|
|
|||
|
mov al,[DMA_Channel]
|
|||
|
and al,00000011b
|
|||
|
out 0D4h,al ; unmask (activate) dma channel
|
|||
|
pop bx
|
|||
|
ret
|
|||
|
|
|||
|
@@DoDMA03:
|
|||
|
mov al,4
|
|||
|
add al,[DMA_Channel]
|
|||
|
out 0Ah,al ; mask reg bit
|
|||
|
|
|||
|
sub al,al
|
|||
|
out 0Ch,al ; clr byte ptr
|
|||
|
|
|||
|
mov al,dh
|
|||
|
add al,[DMA_Channel]
|
|||
|
out 0Bh,al ; set mode reg
|
|||
|
|
|||
|
push dx
|
|||
|
|
|||
|
mov dx,[DMAbaseAdd]
|
|||
|
mov al,bl
|
|||
|
out dx,al ; set base address low
|
|||
|
mov al,bh
|
|||
|
out dx,al ; set base address high
|
|||
|
|
|||
|
inc dx ;point to length
|
|||
|
mov al,cl
|
|||
|
out dx,al ; set length low
|
|||
|
mov al,ch
|
|||
|
out dx,al ; set length high
|
|||
|
|
|||
|
pop dx
|
|||
|
|
|||
|
mov al,dl
|
|||
|
mov dx,[DmaPageReg]
|
|||
|
out dx,al ; set DMA page reg
|
|||
|
|
|||
|
mov al,[DMA_Channel]
|
|||
|
out 0Ah,al ; unmask (activate) dma channel
|
|||
|
pop bx
|
|||
|
ret
|
|||
|
ENDP
|