241 lines
15 KiB
Plaintext
241 lines
15 KiB
Plaintext
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| Zilog |
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| ZZZZZZZ 88888 000 000 22222 |
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| Z 8 8 0 0 0 0 2 2 |
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| Z 8 8 0 0 0 0 0 0 2 |
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| Z 88888 0 0 0 0 0 0 222 |
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| Z 8 8 0 0 0 0 0 0 2 |
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| Z 8 8 0 0 0 0 2 |
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| ZZZZZZZ 88888 000 000 2222222 |
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| Z8002 MICROPROCESSOR Instruction Set Summary |
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| _________ _________ |
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| _| \__/ |_ _____ |
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| <--> AD9 |_|1 40|_| AD0 --> |
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| _| |_ |
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| <--> AD10 |_|2 39|_| AD8 --> |
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| _| |_ |
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| <--> AD11 |_|3 38|_| AD7 <--> |
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| _| |_ |
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| <--> AD12 |_|4 37|_| AD6 <--> |
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| _| |_ |
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| <--> AD13 |_|5 36|_| AD4 <--> |
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| ____ _| |_ |
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| --> STOP |_|6 35|_| AD5 <--> |
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| __ _| |_ |
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| --> Mi |_|7 34|_| AD3 <--> |
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| _| |_ |
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| <--> AD15 |_|8 33|_| AD2 <--> |
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| _| |_ |
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| <--> AD14 |_|9 32|_| AD1 <--> |
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| _| |_ |
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| +5V |_|10 31|_| GND |
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| __ _| |_ |
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| --> VI |_|11 Z8002 30|_| CLOCK <-- |
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| ___ _| |_ __ |
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| --> NVI |_|12 29|_| AS --> |
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| ___ _| |_ |
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| --> NMI |_|13 28|_| RESERVED |
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| _____ _| |_ _ |
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| --> RESET |_|14 27|_| B/W --> |
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| __ _| |_ _ |
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| <-- Mo |_|15 26|_| N/S --> |
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| ____ _| |_ _ |
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| <-- MREQ |_|16 25|_| R/W --> |
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| __ _| |_ _____ |
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| <-- DS |_|17 24|_| BUSAK --> |
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| _| |_ ____ |
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| <-- ST3 |_|18 23|_| WAIT <-- |
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| _| |_ _____ |
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| <-- ST2 |_|19 22|_| BUSRQ <-- |
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| _| |_ |
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| <-- ST1 |_|20 21|_| ST0 --> |
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| |______________________| |
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|Written by Jonathan Bowen |
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| Programming Research Group |
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| Oxford University Computing Laboratory |
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| 8-11 Keble Road |
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| Oxford OX1 3QD |
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| England |
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| Tel +44-865-273840 |
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|Created October 1981 |
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|Updated April 1985 |
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|Issue 1.2 Copyright (C) J.P.Bowen 1985|
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----------------------------------------------------------------
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----------------------------------------------------------------
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|Mnemonic |CZSPDH|Description |Notes |
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|------------+------+----------------------------+-------------|
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|ADCb d,s |****bb|Add with Carry |d=d+s+C |
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|ADDa d,s |****bb|Add |d=d+s |
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|ANDb d,s |-**b--|Logical AND |d=d&s |
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|BITb d,s |-*----|Bit Test |Z=~d<s> |
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|CALL d |------|Call |-[SP]=PC,PC=d|
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|CALR d |------|Call Relative |-[SP]=PC,PC=d|
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|CLRb d |------|Clear |d=0 |
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|COMb d |-**b--|Complement |d=~d |
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|COMFLG f |++++--|Complement Flag |f=~f |
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|CPa d,s |****--|Compare |d-s |
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|CPDb d,s,c|?*?*--|Compare and Decrement |d-s,r=r-1 |
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|CPDRb d,s,c|?*?*--|Compare, Decrement and Rept |CPD till r=0 |
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|CPIb d,s,c|?*?*--|Compare and Increment |d-s,r=r+1 |
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|CPIRb d,s,c|?*?*--|Compare, Increment and Rept |CPI till r=0 |
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|CPSDb d,s,c|?*?*--|Compare String and Decrement|d-s,r=r-1 |
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|CPSDRb d,s,c|?*?*--|Compare String, Dec. and Rep|CPSD till r=0|
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|CPSIb d,s,c|?*?*--|Compare String and Increment|d-s,r=r+1 |
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|CPSIRb d,s,c|?*?*--|Compare String, Inc. and Rep|CPSI till r=0|
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|DAB d |***---|Decimal Adjust Byte |d=BCD format |
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|DECb d,s |-***--|Decrement (s=1-16) |d=d-s |
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|DI i |------|Disable Interrupts | #|
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|DIVl d,s |****--|Divide |d=d/s |
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|DbJNZ r,d |------|Decrement & Jump if Not Zero|r=r-1 |
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|EI i |------|Enable Interrupts | #|
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|EXb d,s |------|Exchange |d<->s |
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|EXTSa d |------|Extend Signs | |
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|HALT |------|Halt | #|
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|pINb d,s |------|(Special) Input |d=s #|
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|INCb d,s |-***--|Increment (s=1-16) |d=d+s |
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|pINDb d,s,r|---*--|(Special) Input and Dec. |d=s,r=r-1 #|
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|pINDRb d,s,r|---1--|(Special) Input, Dec. & Rept|IND till r-0#|
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|pINIb d,s,r|---*--|(Special) Input and Inc. |d=s,r=r+1 #|
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|pINIRb d,s,r|---1--|(Special) Input, Inc. & Rept|INI till r=0#|
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|IRET |??????|Interrupt Return |PS=[SP]+ #|
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|JP cc,d |------|Jump |PC=d |
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|JR cc,d |------|Jump Relative |PC=d |
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|LDa d,s |------|Load |d=s |
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|LDA d,s |------|Load Address |d=EAs |
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|LDAR d,s |------|Load Address Relative |d=EAs |
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|LDCTL d,s |++++++|Load Control |d=s #|
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|LDCTLB d,s |++++++|Load Control Byte |d=s |
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|LDDb d,s,r|---*--|Load and Decrement |d=s,r=r-1 |
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|LDDRb d,s,r|---1--|Load, Decrement and Repeat |LDD till r=0 |
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|LDIb d,s,r|---*--|Load and Increment |d=s,r=r+1 |
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|LDIRb d,s,r|---1--|Load, Increment and Repeat |LDI till r=0 |
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|LDK d,s |------|Load Constant (s=0-15) |d=s |
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|LDM d,s,n|------|Load Multiple (n=1-16) |d=s (n words)|
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|LDPS s |??????|Load Program Status |PS=s #|
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|LDRa d,s |------|Load Relative |d=s |
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|MBIT |??*???|Multi-Micro Bit Test |S=~MI pin #|
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|MREQ d |-**---|Multi-Micro Request |S=available #|
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|MRES |------|Multi-Micro Reset |~MI=high #|
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|MSET |------|Multi-Micro Set |~MO=low #|
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|MULTl d,s |***0--|Multiply |d=d*s |
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|NEGb d |****--|Negate |d=-d |
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|NOP |------|No Operation | |
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|ORb d,s |-**b--|Logical inclusive OR |d=dvs |
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|pOTDRb d,s,r|---1--|(Special) Output, Dec. & Rep|OTD till r=0#|
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|pOTIRb d,s,r|---1--|(Special) Output, Inc. & Rep|OTI till r=0#|
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|pOUTb d,s |------|(Special) Output |d=s #|
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|pOUTDb d,s,r|---*--|(Special) Output and Dec. |d=s,r=r=1 #|
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|pOUTIb d,s,r|---*--|(Special) Output and Inc. |d=s,r=r+1 #|
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|POPl d,s |------|Pop |d=s,[EAs]+ |
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|PUSHl d,s |------|Push |-[EAs],d=s |
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|RESb d,s |------|Reset Bit |d<s>=0 |
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|RESFLG f |++++--|Reset Flag |f=0 |
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|RET cc |------|Return |PC=[SP]+ |
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|RLb d,s |****--|Rotate Left |d=d<-s |
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|RLCb d,s |****--|Rotate Left through Carry |d={C,d}<-s |
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|RLDB ll,s |-*?---|Rotate Left Digit Byte |s={ll,s}<-4 |
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|RRb d,s |****--|Rotate Right |d=s->d |
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|RRCb d,s |****--|Rotate Right through Carry |d=s->{C,d} |
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|RRDB ll,s |-*?---|Rotate Right Digit Byte |s=4->{ll,s} |
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|SBC d,s |****bb|Subtract with Carry |d=d-s-C |
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|SC s |------|System Call (-[SP]={PS,ins})|PS=sys PS #|
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|SDAa d,s |****--|Shift Dynamic Arithmetic |d={1,d,0}<-s |
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----------------------------------------------------------------
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----------------------------------------------------------------
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|Mnemonic |CZSPDH|Description |Notes |
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|------------+------+----------------------------+-------------|
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|SDLa d,s |***?--|Shift Dynamic Logical |d={0,d,0}<-s |
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|SETb d,s |------|Set Bit |d<s>=1 |
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|SETFLG f |++++--|Set Flag |f=1 |
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|SLAa d,s |****--|Shift Left Arithmetic |d={d,0}<-s |
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|SLLa d,s |***?--|Shift Left Logical |d={d,0}<-s |
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|SRAa d,s |***0--|Shift Right Arithmetic |d=s->{1,d} |
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|SRLa d,s |***?--|Shift Right Logical |d=s->{0,d} |
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|SUBa d,s |****bb|Subtract |d=d-s |
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|TCCb cc,d |------|Test Condition Code |If cc d<0>=1 |
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|TESTa d |-***--|Test |dv0 |
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|TRDB d,s,r|-?-*--|Translate and Decrement |d=s[d],r=r-1 |
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|TRDRB d,s,r|-?-1--|Translate, Dec. and Repeat |TRDB till r=0|
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|TRIB d,s,r|-?-*--|Translate and Increment |d=s[d],r=r+1 |
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|TRIRB d,s,r|-?-1--|Translate, Inc. and Repeat |TRIB till r=0|
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|TRTDB s,s,r|-*-*--|Translate, Test and Dec. |RH1=s2[s1],..|
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|TRTDRB s,s,r|-*-*--|Translate, Test, Dec. & Rept|TRTDB till...|
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|TRTIB s,s,r|-*-*--|Translate, Test and Inc. |RH1=s2[s1],..|
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|TRTIRB s,s,r|-*-*--|Translate, Test, Inc. & Rept|TRTIB till...|
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|TSETb d |--*---|Test and Set |{S,d}=d<MSB> |
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|XOR d,s |-**b--|Logical Exclusive OR |d=dxs |
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|------------+------+----------------------------+-------------|
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| FCW |-*01? |Unaffected/affected/reset/set/unknown |
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| |+b |Optionally affected/affected for byte only|
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| C |C |Carry flag (Bit 7) |
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| Z | Z |Zero flag (Bit 6) |
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| S | S |Sign flag (Bit 5) |
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| D | D |Decimal adjust flag (Bit 4) |
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| P/V | P |Parity/Overflow flag (Bit 3) |
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| H | H|Half carry flag (Bit 2) |
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|-------------------+------------------------------------------|
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| #n #nn #nnnn |Immediate data mode (IM, 4/8/16/32-bit) |
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| r |Register addressing mode (R) |
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| @r |Indirect Register mode (IR) |
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| nn |nn| |Direct Addressing mode (DA) |
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| nn[Rn] |Indexed Addressing mode (X, not R0) |
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| $+nn nn |Relative Addressing mode (RA) |
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| RRn[#nn] |Based Addressing mode (BA, not RR0) |
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| RRn[Rn] |Based Indexed addressing mode (BX, not R0)|
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|-------------------+------------------------------------------|
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|AVAL nnnn(,...) |Define Address Value(s) |
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|BVAL n(,...) |Define Byte Value(s) |
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|EVEN |Set program counter to Even address |
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|LVAL nnnn(,...) |Define Long word Value(s) |
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|WVAL nn(,...) |Define Word Value(s) |
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|-------------------+------------------------------------------|
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| FCW |Flag Control Word (16-bit) |
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| PC |Program Counter (32-bit) |
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| PSAP |Program Status Area Pointer (32-bit) |
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| REFRESH |Refresh control register (16-bit) |
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| RLn |Low byte register (8-bit, n=0-7) |
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| RHn |High byte register (8-bit, n=0-7) |
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| Rn |Word register (16-bit, n=0-15) |
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| RRn |Double word register (32-bit, n=0-14,even)|
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| RQn |Quadruple word reg. (64-bit, n=0/4/8/12) |
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| RR14 |Used as stack pointer (32-bit) |
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|-------------------+------------------------------------------|
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| a |Blank, B or L (Word/Byte/Long operation) |
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| b |Blank or B (Word/Byte operation) |
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| c |Condition (r,cc) |
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| cc |Condition Code (F/Z/NZ/C/NC/PL/MI/NE/EQ/ |
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| | OV/NOV/PE/PO/GE/LT/GT/LE/UGE/ULT/UGT/ULE)|
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| d d<X> |Destination/Bit X of Destination |
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| f |Flag(s) (C/Z/S/P/V) |
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| i |Interrupt (VI/NVI) |
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| l |Blank or L (Word/Long word operation) |
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| ll |Link Location (bottom 4 bits of register) |
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| n nn nnnn |Constant expression (8/16/32-bit) |
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| p |Blank or S (Normal/Special operation) |
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| r |Register (RLn/RHn/Rn/RRn/RQn) |
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| s EAs |Source/Effective Address of Source |
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| + - * / |Arithmetic add/subtract/multiply/divide |
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| & ~ v x |Logical AND/NOT/inclusive OR/exclusive OR |
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| <-X X-> |Rotate left/right by X bits |
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| [ ] [ ]+ -[ ] |Indirect address/auto-increment/decrement |
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| { } # |Combination of operands/privileged instr. |
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| |nn| |Short offset (0-255) |
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----------------------------------------------------------------
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