241 lines
15 KiB
Plaintext
241 lines
15 KiB
Plaintext
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| Rockwell |
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| 666 5555555 000 X X |
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| 6 5 0 0 X X |
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| 6 5 0 0 0 X X |
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| 666666 555555 0 0 0 X |
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| 6 6 5 0 0 0 X X |
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| 6 6 5 0 0 X X |
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| 66666 555555 000 X X |
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| 6501/2/3/4/5 MICROPROCESSOR Instruction Set Summary |
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| M M OOOOO SSSSS |
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| MM MM O O S S |
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| M M M M O O S |
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| M M M O O SSSSS |
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| M M O O S |
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| M M O O S S |
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| M M OOOOO SSSSS |
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|Written by Jonathan Bowen |
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| Programming Research Group |
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| Oxford University Computing Laboratory |
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| 8-11 Keble Road |
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| Oxford OX1 3QD |
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| England |
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| Tel +44-865-273840 |
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|Created September 1981 |
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|Updated April 1985 |
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|Issue 1.3 Copyright (C) J.P.Bowen 1985|
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----------------------------------------------------------------
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----------------------------------------------------------------
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|Mnem.|Op|NVBDIZC|A#ZBIRX@|~|Description |Notes |
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|-----+--+-------+--------+-+----------------------+-----------|
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|ADC s|6D|**---**| XxX X |4|Add with Carry |A=A+s+C %|
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|AND s|2D|*----*-| XxX X |4|Logical AND |A=A&s %|
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|ASL d|0E|*----**| xx |6|Arithmetic Shift Left |d={C,d,0}<-|
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|ASLA |0A|*----**|X |2|Arithmetic Shift Left |A={C,d,0}<-|
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|BCC a|90|-------| X |2|Branch if Carry Clear |If C=0(4~)%|
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|BCS a|B0|-------| X |2|Branch if Carry Set |If C=1(4~)%|
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|BEQ a|F0|-------| X |2|Branch if Equal |If Z=1(4~)%|
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|BIT s|2C|**---*-| ** |4|Bit Test |A&s |
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|BMI a|30|-------| X |2|Branch if Minus |If N=1(4~)%|
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|BNE a|D0|-------| X |2|Branch if Not Equal |If Z=0(4~)%|
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|BPL a|10|-------| X |2|Branch if Plus |If N=0(4~)%|
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|BRK |00|--+-1--| X |7|Break (-[S]={PC+2,P})|PC=[FFFEH] |
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|BVC a|50|-------| X |2|Branch if Overflow Clr|If V=0(4~)%|
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|BVS a|70|-------| X |2|Branch if Overflow Set|If V=1(4~)%|
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|CLC |18|------0| X |2|Clear Carry flag |C=0 |
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|CLD |D8|---0---| X |2|Clear Decimal mode |D=0 |
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|CLI |58|----0--| X |2|Clear Int. disable |I=0 |
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|CLV |B8|-0-----| X |2|Clear Overflow flag |V=0 |
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|CMP s|CD|*----**| XxX X |4|Compare |A-s |
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|CPX s|EC|*----**| X** |4|Compare index register|X-s |
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|CPY s|CC|*----**| X** |4|Compare index register|Y-s |
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|DEC d|CE|*----*-| xx |6|Decrement |d=d-1 |
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|DEX |CA|*----*-| X |2|Decrement index reg. |X=X-1 |
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|DEY |88|*----*-| X |2|Decrement index reg. |Y=Y-1 |
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|EOR s|4D|*----*-| XxX X |4|Logical Exclusive OR |A=Axs %|
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|INC d|EE|*----*-| xx |6|Increment |d=d+1 |
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|INX |E8|*----*-| X |2|Increment index reg. |X=X+1 |
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|INY |C8|*----*-| X |2|Increment index reg. |Y=Y+1 |
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|JMP s|4C|-------| * X|3|Jump | !|
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|JSR s|20|-------| * |6|Jump to Subroutine |-[S]=PC+2,!|
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|LDA s|AD|*----*-| XxX X |4|Load Accumulator |A=s %|
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|LDX s|AE|*----*-| Xyy |4|Load index register |X=s %|
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|LDY s|AC|*----*-| Xxx |4|Load index register |Y=s %|
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|LSR d|4E|0----**| xx |6|Logical Shift Right |d=->{0,d,C}|
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|LSRA |4A|0----**|X |2|Logical Shift Right |A=->{0,A,C}|
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|NOP |EA|-------| X |2|No Operation | |
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|ORA s|0D|*----*-| XxX X |4|Logical Inclusive OR |A=Avs |
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|PHA |48|-------| X |3|Push Accumulator |-[S]=A |
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|PHP |08|-------| X |3|Push status register |-[S]=P |
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|PLA |68|-------| X |4|Pull Accumulator |A=[S]+ |
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|PLP |28|*******| X |4|Pull Status Register |P=[S]+ |
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|ROL d|2E|*----**| xx |6|Rotate Left |d={C,d}<- |
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|ROLA |2A|*----**|X |2|Rotate Left Acc. |A={C,A}<- |
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|ROR d|6E|*----**| xx |6|Rotate Right |d=->{C,d} |
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|RORA |6A|*----**|X |2|Rotate Right Acc. |A=->{C,A} |
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|RTI |40|*******| X |6|Return from Interrupt |{PC,P}=[S]+|
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|RTS |60|-------| X |6|Return from Subroutine|PC={[S]+}+1|
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|SBC s|ED|*----**| XxX X |4|Subtract with Carry |A=A-s-C %|
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|SEC |38|------1| X |2|Set Carry flag |C=1 |
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|SED |F8|---1---| X |2|Set Decimal mode |D=1 |
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|SEI |78|----1--| X |2|Set Interrupt disable |I=1 |
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|STA d|8D|-------| xX X |4|Store Accumulator |d=A |
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|STX d|8E|-------| y* |4|Store index register |d=X |
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|STY d|8C|-------| x* |4|Store index register |d=Y |
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|TAX |AA|*----*-| X |2|Transfer Accumulator |X=A |
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|TAY |A8|*----*-| X |2|Transfer Accumulator |Y=A |
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|TSX |BA|*----*-| X |2|Transfer Stack Pointer|X=S |
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|TXA |8A|*----*-| X |2|Transfer Index Reg. |A=X |
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|TXS |9A|-------| X |2|Transfer Index Reg. |S=X |
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|TYA |98|*----*-| X |2|Transfer Index Reg. |A=Y |
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|-----+--+-------+--------+-+----------------------------------|
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| |XX| | |X|Hexadecimal opcode/no. of cycles |
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|--------+-------+--------+-+----------------------------------|
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| |- | | |Flag unaffected |
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| |* | | |Flag affected |
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| |0 | | |Flag reset |
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| |1 | | |Flag set |
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| |+ | | |Flag set on stack |
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|--------+-------+--------+-+----------------------------------|
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| N |N | | |Negative status (Bit 7) |
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| V | V | | |Overflow status (Bit 6) |
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| B | B | | |Break command indicator (Bit 4) |
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| D | D | | |Decimal mode control (Bit 3) |
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| I | I | | |Interrupt disable control (Bit 2) |
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| Z | Z | | |Zero status (Bit 1) |
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| C | C| | |Carry status (Bit 0) |
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----------------------------------------------------------------
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----------------------------------------------------------------
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|Mnemonic |A#ZBIRX@|Description |Opcode| ~s |
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|----------------+--------+------------------------+------+----|
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| |X |All mode(s) valid | | |
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| |* |Non-indexed mode valid | | |
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| |x |X/non-indexed mode valid| | |
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| |y |Y/non-indexed mode valid| | |
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|----------------+--------+------------------------+------+----|
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| | |Add XXH to opcode | +XXH | |
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| | |Subtract XXH from opcode| -XXH | |
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| | |Add X to no. of cycles | | +X |
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| | |Subtract X from cycles | | -X |
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|----------------+--------+------------------------+------+----|
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| A |A |Accumulator | | |
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| #n | # |Immediate | -04H | -2 |
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| <n | * |Zero page | -08H | -1 |
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| n | * |Zero page (DIRECT mode) | -08H | -1 |
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| n,X | x |Zero page indexed (X) | +08H | +0 |
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| n,Y | y |Zero Page indexed (Y) | +08H | +0 |
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| >nn | * |Absolute | +00H | +0 |
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| nn | * |Absolute (EXTEND mode) | +00H | +0 |
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| nn,X | x |Absolute indexed (X) | +10H | +0 |
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| nn,Y | y |Absolute indexed (Y) | +0CH | +0 |
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| LDX nn,Y | y | ditto | +10H | +0 |
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| | I |Implicit | | |
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| a | R |Relative(PC=PC+1+offset)| | +2 |
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| [nn,X] | x |Indexed indirect (X) | -0CH | +2 |
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| [nn],Y | y |Indirect indexed (Y) | +04H | +1 |
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| [nn] | @|Absolute indirect | +20H | +2 |
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|-------------------------+------------------------------------|
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|BYTE n(,...) |Byte(s) (8-bit) |
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|BYTE 'string'(,...) |Byte text string(s) |
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|DIRECT |Zero page addressing mode |
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|EXTEND |Absolute addressing mode |
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|RMB nn(,...) |Reserve Memory Bytes |
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|WORD nn(,...) |Word(s) (16-bit) |
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|-------------------------+------------------------------------|
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| A |Accumulator (8-bit) |
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| P |Status Register (8-bit) |
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| PC |Program Counter (16-bit) |
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| S |Stack Pointer (9-bit, MSB=1) |
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| X Y |Index Registers X and Y (8-bit) |
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|-------------------------+------------------------------------|
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| a |Relative Address (-128 to +127) |
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| d |Destination |
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| n |8-bit expression (0 to 255) |
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| nn |16-bit expression (0 to 65535) |
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| s |Source |
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| string |String of ASCII characters |
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|-------------------------+------------------------------------|
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| + |Arithmetic addition |
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| - |Arithmetic subtraction |
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| * |Arithmetic multiplication |
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| / |Arithmetic division |
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| & |Logical AND |
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| ~ |Logical NOT |
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| v |Logical inclusive OR |
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| x |Logical exclusive OR |
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| <- |Rotate left |
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| -> |Rotate right |
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| [ ] |Indirect addressing |
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| [ ]+ |Indirect addressing, auto-increment |
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| -[ ] |Auto-decrement, indirect addressing |
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| { } |Combination of operands |
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| $ |Program counter content |
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| % |~s = ~s+1 if crossing page boundary |
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| ! |PC = effective address of source |
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|-------------------------+------------------------------------|
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|0000H to 00FFH |Page 0 (see zero page addressing) |
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|0100H to 01FFH |Page 1 (stack area, 01FFH = start) |
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|XX00H to XXFFH |Page n (where n=XXH) |
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|FFFAH to FFFBH |Non maskable interrupt (NMI) vector |
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|FFFCH to FFFDH |Reset (RES) vector |
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|FFFEH to FFFFH |Interrupt Request (IRQ) vector |
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|FFFEH to FFFFH |Break command vector (see BRK) |
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|-------------------------+------------------------------------|
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| 6501/6502 |16 address lines, 65536 bytes max. |
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| 6503/6505 |13 address lines, 8192 bytes max. |
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| 6504 |12 address lines, 4096 bytes max. |
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----------------------------------------------------------------
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