81 lines
3.4 KiB
Plaintext
81 lines
3.4 KiB
Plaintext
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I found this document somewhere on a gopher archive in an Apple2's
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programming directory and I think this could be very useful information
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for example for emulator writers :)
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2-Nov-1994 Ivo van Poorten <ipoorten=www@cs.vu.nl>
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With all the books on 6502 programming, and all the years that the 6502 has
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been around and popular, you'd think that any quirks would have been well
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documented by now. But nooooo!
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So... for those of you involved in assembler or machine-language programming,
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here are some 6502 booby-traps -- those marked with * are supposedly fixed
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in the CMOS parts such as 65C02 and 65C102 (but not the C-64's 6510).
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---------
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o Return address pushed on the stack by JSR is one less than actual next
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instruction. RTS increments PC after popping. RTI doesn't.
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o The status bits pushed on the stack by PHP have the breakpoint bit set.
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o *The D (decimal mode) flag is not defined after RESET.
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o *The D (decimal mode) flag is not cleared by interrupts.
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o *The ADC and SBC instructions don't set N,V, and Z status bits if decimal
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mode is on. C status is set correctly.
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o *An indirect JMP (xxFF) will fail because the MSB will be fetched from
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address xx00 instead of page xx+1.
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o *If an interrupt occurs on a BRK instruction, the breakpoint is ignored.
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o *The ROR instruction didn't exist in the very earliest (pre-'77) chips.
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o *Undefined op-codes do strange things, some lock up the CPU.
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Unlike most microprocessors, the 6502 does not make memory accesses on an
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"as needed" basis. It always does a fetch or store on every single clock
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cycle. There are a few cases, though, where there isn't anything to be
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fetched or stored, and a "garbage" fetch or store occurs. This is mainly
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of importance with the memory-mapped I/O devices:
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o *When adding a carry to the MSB of an address, a fetch occurs at a garbage
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address. The CMOS chips refetch the last byte of the instruction.
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o *When doing a fetch-modify-store instruction (INC, DEC, ASL, LSR, ROL,
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ROR) garbage is stored into the location during the "modify" cycle...
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followed by the "real" store cycle which stores the correct data. The
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CMOS chips do a second fetch instead of a garbage store.
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These aren't really "bugs", but there are some instructions that just seem
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like they ought to be there, but aren't:
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o *INC A and DEC A.
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o *BRA relative. Unconditional branch.
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o *BIT #immediate. The CMOS chips also have BIT absolute,X and
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BIT zeropage,X.
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o STX absolute,Y and STY absolute,X. How come LDX and LDY can use these
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addressing modes, but the matching store instructions can't?
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o SEV. Set overflow bit. Probably not really useful, but you can set and
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clear all of the other status bits, and there *is* a CLV.
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o Personally, I'd also like to have "Clear A" and "Test A" instructions.
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These would be twice as fast and half as big as LDA #0 and CMP #0.
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Ironically, the CMOS chips have an STZ (Store Zero) instruction which
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can clear a memory location, but still can't clear the Accumulator.
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o I'd also like to have BSR relative. A subroutine call that's relocatable.
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*Fixed in the CMOS versions (65C02, 65C102, etc.)
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-------------------------------------------------------------------------------
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