79 lines
3.7 KiB
Plaintext
79 lines
3.7 KiB
Plaintext
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MiniSport Laptop Hacker - Vol 10, 4 Apr 1993
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Copyright(C) 1993 by Brian Mork.
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>>> ADMIN
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Previous issues are 1-5,6A,6B, and 7-9. I received some questions about
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spuratic receipt of all issues. I've gotten feedback that some sysops were
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killing any messages over 3K. With all the routing headers added to the
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top, that was pretty limiting! I'm now splitting the issues into two
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parts. That should grease the path to your particular QTH. Thanks to
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N7FTM, W9NQP, WB8HQS, N8QYG, N9ADS, W5SYT for input.
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>>> EXTERNAL DRIVE PINOUT
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Here's the external floppy pinout. Thanks, Steve (W9NWP). Pin numbering is
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like a Scotch-flex header: 1 3 5 7 9 11 13 15 17 19
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2 4 6 8 10 12 14 16 18 20 or rotate CW:
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2 _Side Select 1 _Disk Change
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4 GND 3 _Read Data
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6 _Track Zero 5 _Write Protect
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8 _Write Enable 7 _Index
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10 GND 9 _Write Data
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12 GND 11 _Step
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14 _Drive Select 2 13 _Direction Select
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16 _Motor ON 15 _RPM
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18 Vcc 17 Vcc
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20 GND 19 GND
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The underscore character indicates negated signals (true when low).
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>>> COM I/O ARCHITECTURE
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Continuing where Volume 8 left off...
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Interrupt Enable Register (IER) at address (BASE+1)
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---------------------------------------------------
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Only the lower 4 bits are used. The high four bits are permanently at
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zero. The four used bits indicate which conditions will cause the UART to
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interrupt the computer.
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CAUTION: BASE+1 will access this register if and only if the most signifi-
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cant bit of the LCR (BASE+3) is zero.
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Bit 0: Received Data Available. Set this to 1 if you want the computer
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interrupted when new data has arrived. This bit is reset to zero
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upon completion of the associated interrupt service routine.
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Bit 1: Transmitter Register Empty. Set this to 1 if you want to be inter-
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rupted when the UART is ready to receive another character to trans-
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mit. This bit is reset to 0 immediately upon reading the IIR regis-
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ter.
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Bit 2: Receiver Line Status. Set to 1 if you want the UART to interrupt
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when any of the following occur: Overrun Error, Parity Error, Fram-
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ing Error, or Break Interrupt. Reset to 0 upon completion of the
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associated interrupt service routine.
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Bit 3: Modem Status. Set to 1 if you want the UART to interrupt the comput-
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er when it receives any of: Clear to Send, Data Set Ready, Ring In-
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dicator or Received Line Signal Detect. This bit is reset to 0 upon
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completion of the associated interrupt service routine.
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Bit 4-7: Always 0.
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Interrupt Identification Register (IIR) at address (BASE+2)
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-----------------------------------------------------------
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The 8250 prioritizes the four types of interrupts discussed under the IER
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section in the following order from top priority to lowest: RLS, RDA, TRE,
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and MS. The following three bits indicate the highest pending interrupt.
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Bit 0: When 0, some interrupt is pending.
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Bits 1,2: Indicate the type of the highest priority pending interrupt. RLS
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gives 11, RDA gives 10, TRE gives 01, MS gives 00.
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Bits 3-7: Always 0.
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And a request: If anybody has an I/O address map for the IBM-PC environent,
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addresses 00H up to 0FFH, I would love to get a copy. Packet me the info
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directly, or maybe mail me a photocopy of something. Thank you!.
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73, Brian Mork (Opus-OVH) KA9SNF@wb7nnf.#spokn.wa.usa
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Internet ka9snf@jupiter.spk.wa.us
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6006-B Eaker, Fairchild, WA 99011
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