65 lines
2.0 KiB
Plaintext
65 lines
2.0 KiB
Plaintext
|
(r) this line goes to the ROM only.
|
||
|
|
(s) this line is Shared between the ROM, MMC/chip, and Nintendo
|
||
|
|
(n) this line connects to the NES cart edge only, and not the ROM
|
||
|
|
(w) this line connects to the WRAM only and nowhere else
|
||
|
|
|
||
|
|
|
||
|
|
MMC3 Chip: (44 pin QFP) [Made by Kevin Horton (khorton@iquest.net)]
|
||
|
|
----------
|
||
|
|
Comes in three types: 'MMC3A', 'MMC3B', and 'MMC3C'
|
||
|
|
|
||
|
|
33 23
|
||
|
|
| |
|
||
|
|
.-------.
|
||
|
|
34-| |-22
|
||
|
|
| MMC3B |
|
||
|
|
44-| |-12
|
||
|
|
\-------'
|
||
|
|
| |
|
||
|
|
1 11
|
||
|
|
|
||
|
|
|
||
|
|
Pin# Function Pin# Function
|
||
|
|
---- -------- ---- --------
|
||
|
|
|
||
|
|
1 - ??? *1 23 - PRG A17 (r)
|
||
|
|
2 - CHR A10 (r) 24 - PRG A13 (n)
|
||
|
|
3 - CHR A12 (n) 25 - PRG A18 (r)
|
||
|
|
4 - CHR A11 (n) 26 - PRG /CE (r)
|
||
|
|
5 - CHR A10 (n) 27 - +5V
|
||
|
|
6 - GND 28 - GND
|
||
|
|
7 - CHR A13 (r) 29 - M2
|
||
|
|
8 - CHR A14 (r) 30 - WRAM /CE (w)
|
||
|
|
9 - CHR A12 (r) 31 - PRG D7 (s)
|
||
|
|
10 - CIRAM A10 (n)*32 - PRG A0 (s)
|
||
|
|
11 - CHR A15 (r) 33 - PRG D6 (s)
|
||
|
|
12 - CHR A17 (r) 34 - PRG D0 (s)
|
||
|
|
13 - /IRQ 35 - PRG D5 (s)
|
||
|
|
14 - PRG /CE (n) 36 - PRG D1 (s)
|
||
|
|
15 - GND 37 - PRG D4 (s)
|
||
|
|
16 - ??? *2 38 - PRG D2 (s)
|
||
|
|
17 - PRG R/W (n) 39 - PRG D3 (s)
|
||
|
|
18 - PRG A15 (r) 40 - GND
|
||
|
|
19 - PRG A13 (r) 41 - WRAM CE (w)
|
||
|
|
20 - PRG A14 (n) 42 - WRAM /WE (w)
|
||
|
|
21 - PRG A16 (r) 43 - CHR A11 (r)
|
||
|
|
22 - PRG A14 (r) 44 - CHR A16 (r)
|
||
|
|
|
||
|
|
NOTES:
|
||
|
|
|
||
|
|
*: On Gauntlet, this is unused.
|
||
|
|
|
||
|
|
|
||
|
|
*1: PINS 1 & 2. Sometimes these are connected together. If they are not,
|
||
|
|
pin 1 is left floating.
|
||
|
|
|
||
|
|
*2: PIN 16. Sometimes this is connected to ground. Other times it is left
|
||
|
|
floating.
|
||
|
|
|
||
|
|
It seems that pins 1,2 & 16 are related; pins 1 & 2 are shorted as are pins
|
||
|
|
15 and 16. Or else pisn 1 & 2 are left open as well as 15 & 16. I've never
|
||
|
|
seen say, pins 1 & 2 shorted while pin 16 was open or vice-versa. I suspect
|
||
|
|
they relate to extra RAM in the CHR section.
|
||
|
|
|
||
|
|
|