91 lines
2.7 KiB
NASM
91 lines
2.7 KiB
NASM
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; ====================================================================
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; DR 6502 AER 201S Engineering Design 6502 Execution Simulator
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; ====================================================================
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;
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; Supplementary Notes By: M.J.Malone
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;
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;
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; Project Board Test Program
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; ==========================
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; This program sets Port A to input and Port B to output on both VIAs.
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; The program reads from Port A and writes to Port B making the computer
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; act as a giant wire. If you connect Port A, bit 0 to ground, bit 0 of
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; Port B will go to ground. If you connect bit 0 of Port A to 5 volts or do
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; not connect it to anything then Port B bit 0 will be 5 volts. Note that if
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; an input port (Port A in this case) is not connected to anything then it
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; will default to being 5 volts because of an internal pull up resistor in
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; the VIA.
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;
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; Note that the data read from Port A is written to memory and read back
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; to test the RAM as well.
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;
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; If a board completes this test then the following components are known to
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; work for the following reasons.
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; Proven
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; Component: Reason:
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; 6502 It could not be running the code if it were not working
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; 6522s The ports would not read or write correctly otherwise
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; EPROM If the program is in EPROM and is running then the EPROM is OK
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; RAM Because the data read on Port A is reflected correctly on B
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; 74HC74 Necessary to the system clock and therefore functioning
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; 74HC139 Necessary to the address select of VIA, EPROM and RAM
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; 74xx04 Necessary to the clock, R/W and address select functions
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; Reset The system must be resetting properly if the program runs.
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;
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; If the test fails then the above can be used in reverse for troubleshooting.
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;
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.ORG $E000
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SEI ; INITIALIZING THE STACK POINTER
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LDX #$FF
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TXS
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;
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LDX #$00 ; Initial delay to allow Spurious Resets to
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LDY #$00 ; subside.
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Delay DEX
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BNE Delay
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DEY
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BNE Delay
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;
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PORTA1 = $A001
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PORTB1 = $A000
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DDRA1 = $A003
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DDRB1 = $A002
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;
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PORTA2 = $8001
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PORTB2 = $8000
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DDRA2 = $8003
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DDRB2 = $8002
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;
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page 2
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lda #%11111111 ; Port Bs to outputs
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sta DDRB1
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sta DDRB2
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lda #%00000000 ; Port As to inputs
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sta DDRA1
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sta DDRA2
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Top lda PORTA1 ; VIA 1: Port A ==> RAM ==> Port B
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sta $ab
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lda $ab
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sta PORTB1
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;
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lda PORTA2 ; VIA 2: Port A ==> RAM ==> Port B
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sta $ae
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lda $ae
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sta PORTB2
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;
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jmp Top
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;
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.ORG $FFFC
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.WORD $E000
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.END
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