241 lines
15 KiB
Plaintext
241 lines
15 KiB
Plaintext
|
----------------------------------------------------------------
|
||
|
|
| |
|
||
|
|
| |
|
||
|
|
| Digital Equipment Corporation |
|
||
|
|
| |
|
||
|
|
| PPPPPP DDDDD PPPPPP 1 1 |
|
||
|
|
| P P D D P P 11 11 |
|
||
|
|
| P P D D P P 1 1 |
|
||
|
|
| PPPPPP D D PPPPPP XXX 1 1 |
|
||
|
|
| P D D P 1 1 |
|
||
|
|
| P D D P 1 1 |
|
||
|
|
| P DDDDD P 111 111 |
|
||
|
|
| |
|
||
|
|
| PDP-11 Processor Instruction Set Summary |
|
||
|
|
| as implemented on the HP64000 |
|
||
|
|
| |
|
||
|
|
| |
|
||
|
|
| |
|
||
|
|
| |
|
||
|
|
| |
|
||
|
|
| |
|
||
|
|
| |
|
||
|
|
|XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX|
|
||
|
|
|XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX|
|
||
|
|
|XXXXX X XXX XXX XXXXXXXX XXX XXX XX XXXX XXXXXXXX XXX XXX|
|
||
|
|
|XXXXX X XXXXXXXX XXXXXXXX XXXXXXXX XX XXXX XXXXXXXX XXX XXX|
|
||
|
|
|XX X XXX XXX XX XX XXX XXX X XXX XX XX XXX XXX|
|
||
|
|
|X XX X XXX XXX X XX X XXX XXX XX XXXX XXXXX X XXX XXX|
|
||
|
|
|X XX X XXX XXX X XX X XXX XXX XX XXXX XX X XXX XXX|
|
||
|
|
|X XX X XXX XXX X XX X XXX XXX XX XXXX X XX X XXX XXX|
|
||
|
|
|XX X XXX XXX XX X XXX XXX XXX XX XX X XXX XXX|
|
||
|
|
|XXXXXXXX XXXXXXXX XXXXX X XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX|
|
||
|
|
|XXXXXXXX XXXXXXXX XX XX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX|
|
||
|
|
|XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX|
|
||
|
|
| |
|
||
|
|
| |
|
||
|
|
| |
|
||
|
|
| |
|
||
|
|
| |
|
||
|
|
| |
|
||
|
|
| |
|
||
|
|
|----------------------- XXXX ---------------------------------|
|
||
|
|
|********************* XXXX #######################|
|
||
|
|
|***************** XXXX ##################|
|
||
|
|
|*************** XXXX ################|
|
||
|
|
|************* XXXX ##############|
|
||
|
|
|************ XXXX #############|
|
||
|
|
|*********** XXXXXXXXXXXX XXXXXXXXXXX ############|
|
||
|
|
|********** XXXX XXXX XXXX XXXX ###########|
|
||
|
|
|********** XXXX XXXX XXXX XXXX ###########|
|
||
|
|
|********** XXXX XXXX XXXX XXXX ###########|
|
||
|
|
|********** XXXX XXXX XXXX XXXX ###########|
|
||
|
|
|*********** XXXX XXXX XXXXXXXXXXXX ############|
|
||
|
|
|************ XXXX #############|
|
||
|
|
|************* XXXX ##############|
|
||
|
|
|*************** XXXX ################|
|
||
|
|
|***************** XXXX ##################|
|
||
|
|
|********************** XXXX #######################|
|
||
|
|
|----------------------- XXXX ---------------------------------|
|
||
|
|
| |
|
||
|
|
| |
|
||
|
|
| |
|
||
|
|
| |
|
||
|
|
| |
|
||
|
|
| |
|
||
|
|
| |
|
||
|
|
| |
|
||
|
|
|Written by Jonathan Bowen |
|
||
|
|
| Programming Research Group |
|
||
|
|
| Oxford University Computing Laboratory |
|
||
|
|
| 8-11 Keble Road |
|
||
|
|
| Oxford OX1 3QD |
|
||
|
|
| England |
|
||
|
|
| |
|
||
|
|
| Tel +44-865-273840 |
|
||
|
|
| |
|
||
|
|
|Created April 1982 |
|
||
|
|
|Updated April 1985 |
|
||
|
|
|Issue 1.2 Copyright (C) J.P.Bowen 1985|
|
||
|
|
----------------------------------------------------------------
|
||
|
|
----------------------------------------------------------------
|
||
|
|
|Mnemonic |Opcode|NZVC|Description |Notes |
|
||
|
|
|---------+------+----+--------------------------+-------------|
|
||
|
|
|ADCb d |B055DD|****|Add Carry |d=d+C |
|
||
|
|
|ADD s,d |06SSDD|****|Add |d=s+d |
|
||
|
|
|ASH s,r |072RSS|****|Arithmetic Shift |r=r*2^s(EIS)#|
|
||
|
|
|ASHC s,r |073RSS|****|Arithmetic Shift Combined | (EIS)#|
|
||
|
|
|ASLb d |B063DD|****|Arithmetic Shift Left |d=d*2 |
|
||
|
|
|ASRb d |B062DD|****|Arithmetic Shift Right |d=d/2 |
|
||
|
|
|BCC a |1030XX|----|Branch if Carry Clear |If C=0 |
|
||
|
|
|BCS a |1034XX|----|Branch if Carry Set |If C=1 |
|
||
|
|
|BEQ a |0014XX|----|Branch if Equal |If Z=0 |
|
||
|
|
|BGE a |0020XX|----|Branch if Greater or Equal|If NxV=0 |
|
||
|
|
|BGT a |0030XX|----|Branch if Greater Than |If Zv{NxV}=0 |
|
||
|
|
|BICb s,d |B4SSDD|**0-|Bit Clear |d=d&{~s} |
|
||
|
|
|BISb s,d |B5SSDD|**0-|Bit Set (OR) |d=dvs |
|
||
|
|
|BITb s,d |B3SSDD|**0-|Bit Test (AND) |d&s |
|
||
|
|
|BHI a |1010XX|----|Branch if Higher |If CvZ=0 |
|
||
|
|
|BHIS a |1030XX|----|Branch if Higher or Same |If C=0 |
|
||
|
|
|BLE a |0034XX|----|Branch if Less or Equal |If Zv{NxV}=1 |
|
||
|
|
|BLT a |0024XX|----|Branch if Less Than |If NxV=1 |
|
||
|
|
|BLO a |1034XX|----|Branch if Lower |If C=1 |
|
||
|
|
|BLOS a |1014XX|----|Branch if Lower or Same |If CvZ=1 |
|
||
|
|
|BMI a |1004XX|----|Branch if Minus |If N=1 |
|
||
|
|
|BNE a |0010XX|----|Branch if Not Equal |If Z=1 |
|
||
|
|
|BPL a |1000XX|----|Branch if Plus |If N=0 |
|
||
|
|
|BPT |000003|----|Breakpoint Trap |Vector at 14 |
|
||
|
|
|BR a |0004XX|----|Branch |PC=PC+2*XX |
|
||
|
|
|BVC a |1020XX|----|Branch if Overflow Clear |If V=0 |
|
||
|
|
|BVS a |1024XX|----|Branch if Overflow Set |If V=1 |
|
||
|
|
|CALL d |0047DD|----|Call subroutine | (= JSR PC,d)|
|
||
|
|
|CCC |000257|0000|Clear all Condition Codes |{C,N,V,Z}=0 |
|
||
|
|
|CLC |000241|---0|Clear Carry |C=0 |
|
||
|
|
|CLN |000250|0---|Clear Negative |N=0 |
|
||
|
|
|CLRb d |B050DD|0100|Clear |d=0 |
|
||
|
|
|CLV |000242|--0-|Clear Overflow |V=0 |
|
||
|
|
|CLZ |000244|-0--|Clear Zero |Z=0 |
|
||
|
|
|CMPb s,d |B2SSDD|****|Compare |s-d |
|
||
|
|
|COMb d |B051DD|**01|Complement |d=~d |
|
||
|
|
|DECb d |B053DD|***-|Decrement |d=d-1 |
|
||
|
|
|DIV s,r |071RSS|****|Divide |r=r/s (EIS)#|
|
||
|
|
|EMT t |1040TT|----|Emulator Trap |Vector at 30 |
|
||
|
|
|FADD r |07500R|**00|Floating Add | (FIS)#|
|
||
|
|
|FDIV r |07503R|**00|Floating Divide | (FIS)#|
|
||
|
|
|FMUL r |07502R|**00|Floating Multiply | (FIS)#|
|
||
|
|
|FSUB r |07501R|**00|Floating Subtract | (FIS)#|
|
||
|
|
|HALT |000000|----|Halt | |
|
||
|
|
|INCb d |B052DD|***-|Increment |d=d+1 |
|
||
|
|
|IOT |000004|----|Input/Output Trap |Vector at 20 |
|
||
|
|
|JMP d |0001DD|----|Jump |PC=d |
|
||
|
|
|JSR r,d |004RDD|----|Jump to Subroutine |r=PC,PC=d |
|
||
|
|
|MARK n |0064NN|----|Mark stack |RTS aid #|
|
||
|
|
|MFPD s |1065SS|----|Move From Previous Data | #|
|
||
|
|
|MFPI s |0065SS|----|Move From Previous Instr. | #|
|
||
|
|
|MFPS d |1067DD|**0-|Move From Processor Status|d=PS (byte)#|
|
||
|
|
|MOVb s,d |B1SSDD|**0-|Move |d=s |
|
||
|
|
|MTPD d |1066DD|----|Move To Previous Data | #|
|
||
|
|
|MTPI d |0066DD|----|Move To Previous Instr. | #|
|
||
|
|
|MTPS s |1064SS|****|Move To Processor Status |PS=s (byte)#|
|
||
|
|
|MUL s,r |070RSS|**0*|Multiply |r=r*s (EIS)#|
|
||
|
|
|NEGb d |B054DD|****|Negate |d=-d |
|
||
|
|
|NOP |000240|----|No Operation | |
|
||
|
|
|RESET |000005|----|Reset external bus | |
|
||
|
|
|RETURN |000207|----|Return from subroutine | (= RTS PC)|
|
||
|
|
|ROLb d |B061DD|****|Rotate Left |d={C,d}<- |
|
||
|
|
|RORb d |B060DD|****|Rotate Right |d=->{C,d} |
|
||
|
|
|RTI |000002|----|Return from Interrupt |{PC,PS}=[SP]+|
|
||
|
|
|RTS r |00020R|----|Return from Subroutine |PC=r,r=[SP]+ |
|
||
|
|
|RTT |000006|----|Return from Trace trap |No T trap #|
|
||
|
|
|SBCb d |B056DD|****|Subtract Carry |d=d-C |
|
||
|
|
|SCC |000277|1111|Set all Condition Codes |{C,N,V,Z}=1 |
|
||
|
|
|SEC |000261|---1|Set Carry |C=1 |
|
||
|
|
|SEN |000270|1---|Set Negative |N=1 |
|
||
|
|
|SEV |000262|--1-|Set Overflow |V=1 |
|
||
|
|
|SEZ |000264|-1--|Set Zero |Z=1 |
|
||
|
|
|SOB r,a |077RNN|----|Subtract One and Branch |PC=PC-2*NN #|
|
||
|
|
|SPL n |00023N|----|Set Priority Level |PS[7-5]=N #|
|
||
|
|
|SUB s,d |16SSDD|****|Subtract |d=d-s |
|
||
|
|
|SWAB d |0003DD|**00|Swap Bytes | |
|
||
|
|
----------------------------------------------------------------
|
||
|
|
----------------------------------------------------------------
|
||
|
|
|Mnemonic |Opcode|NZVC|Description |Notes |
|
||
|
|
|---------+------+----+--------------------------+-------------|
|
||
|
|
|SXT d |0067DD|-*0-|Sign Extend |d=0 or -1 #|
|
||
|
|
|TRAP t |1044TT|----|Trap |Vector at 34 |
|
||
|
|
|TSTb d |B055DD|**00|Test |d |
|
||
|
|
|WAIT |000001|----|Wait for interrupt | |
|
||
|
|
|XOR r,d |074RDD|**0-|Exclusive OR |d=dxr #|
|
||
|
|
|---------+------+----+----------------------------------------|
|
||
|
|
| | B| |0 for word, 1 for byte (1 bit) |
|
||
|
|
| | DD| |Destination field (6 bits) |
|
||
|
|
| | N| |Number (3 bits) |
|
||
|
|
| | NN| |Number (6 bits) |
|
||
|
|
| | R| |Register (3 bits, R0-5/SP/PC) |
|
||
|
|
| | SS| |Source field (6 bits) |
|
||
|
|
| | TT| |Number (8 bits) |
|
||
|
|
| | XX| |Offset (8 bits, -128 to +127) |
|
||
|
|
|----------------+----+----------------------------------------|
|
||
|
|
| PSW |-*01|Flag unaffected/affected/reset/set |
|
||
|
|
| T | |Trace trap (Bit 4) |
|
||
|
|
| N |N |Negative (Bit 3) |
|
||
|
|
| Z | Z |Zero (Bit 2) |
|
||
|
|
| V | V |Overflow (Bit 1) |
|
||
|
|
| C | C|Carry (Bit 0) |
|
||
|
|
|---------------------+----------------------------------------|
|
||
|
|
| r |Register (mode 0) |
|
||
|
|
| @r or [r] |Register deferred (mode 1) |
|
||
|
|
| [r]+ |Autoincrement (mode 2) |
|
||
|
|
| @[r]+ |Autoincrement deferred (mode 3) |
|
||
|
|
| -[r] |Autodecrement (mode 4) |
|
||
|
|
| @-[r] |Autodecrement deferred (mode 5) |
|
||
|
|
| nn[r] |Index (mode 6) |
|
||
|
|
| @nn[r] |Index deferred (mode 7) |
|
||
|
|
| #nn |Immediate (mode 2, r=PC) |
|
||
|
|
| @#nn |Absolute (mode 3, r=PC) |
|
||
|
|
| nn |Relative (mode 6, r=PC) |
|
||
|
|
| @nn |Relative deferred (mode 7, r=PC) |
|
||
|
|
|---------------------+----------------------------------------|
|
||
|
|
|ASCII "string"(,...)|ASCII string |
|
||
|
|
|ASCIZ "string"(,...)|ASCII string with Zero byte terminator |
|
||
|
|
|ASECT |Absolute Section (equivalent to ORG 0) |
|
||
|
|
|BLKB expr |Block Bytes (8-bit) |
|
||
|
|
|BLKW expr |Block Words (16-bit) |
|
||
|
|
|BYTE expr(,...) |Byte(s) (8-bit) |
|
||
|
|
|EOT |End Of Tape (ignored) |
|
||
|
|
|ERROR string |User-invoked Error |
|
||
|
|
|EVEN |Set current location to Even address |
|
||
|
|
|FLT2 fp(,...) |2-word Floating point number(s) |
|
||
|
|
|FLT4 fp(,...) |4-word Floating point number(s) |
|
||
|
|
|ODD |Set current location to Odd address |
|
||
|
|
|PRINT string |User-invoked warning |
|
||
|
|
|RAD50 "string"(,...)|Radix 50 string (space,A-Z,$,.,?,0-9) |
|
||
|
|
|WORD expr(,...) |Word(s) (16-bit) |
|
||
|
|
|---------------------+----------------------------------------|
|
||
|
|
| EIS |Extended Instruction Set (fixed point) |
|
||
|
|
| FIS |Floating point Instruction Set |
|
||
|
|
| Rn |General Register (16-bit, n=0-7) |
|
||
|
|
| SP |Stack Pointer (16-bit, R6) |
|
||
|
|
| PC |Program Counter (16-bit, R7) |
|
||
|
|
| PS |Processor Status (16-bit) |
|
||
|
|
|---------------------+----------------------------------------|
|
||
|
|
| a |Relative address |
|
||
|
|
| b |Blank or B for word or byte operand(s) |
|
||
|
|
| d |Destination operand |
|
||
|
|
| n |Register number (0 to 5) |
|
||
|
|
| nn |16-bit expression (0 to 65535) |
|
||
|
|
| r |Register (Rn,SP,PC) |
|
||
|
|
| s |Source operand |
|
||
|
|
| t |Trap number (0 to 255) |
|
||
|
|
|---------------------+----------------------------------------|
|
||
|
|
| + - |Add/subtract |
|
||
|
|
| * / |Multiply/divide |
|
||
|
|
| ^ |Power |
|
||
|
|
| & ~ |Logical AND/NOT |
|
||
|
|
| v x |Logical inclusive/exclusive OR |
|
||
|
|
| <- -> |Rotate left/right |
|
||
|
|
| { } |Combination of operands |
|
||
|
|
| # |Not applicable to all processors |
|
||
|
|
| (,...) |Optional list separated by commas |
|
||
|
|
----------------------------------------------------------------
|