241 lines
15 KiB
Plaintext
241 lines
15 KiB
Plaintext
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| RCA |
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| 1 88888 000 22222 |
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| 11 8 8 0 0 2 2 |
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| 1 8 8 0 0 0 2 |
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| 1 88888 0 0 0 222 |
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| 1 8 8 0 0 0 2 |
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| 1 8 8 0 0 2 |
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| 111 88888 000 2222222 |
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| CDP1802 COSMAC Microprocessor Instruction Set Summary |
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| _________ _________ |
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| _| \__/ |_ |
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| --> CLOCK |_|1 40|_| Vdd |
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| ____ _| |_ ____ |
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| --> WAIT |_|2 39|_| XTAL --> |
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| _____ _| |_ ______ |
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| --> CLEAR |_|3 38|_| DMA IN <-- |
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| _| |_ _______ |
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| <-- Q |_|4 37|_| DMA OUT <-- |
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| _| |_ _________ |
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| <-- SC1 |_|5 36|_| INTERRUPT <-- |
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| _| |_ ___ |
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| <-- SC0 |_|6 35|_| MWR <-- |
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| ___ _| |_ |
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| <-- MRD |_|7 34|_| TPA --> |
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| _| |_ |
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| <--> BUS 7 |_|8 33|_| TPB --> |
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| _| |_ |
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| <--> BUS 6 |_|9 32|_| MA7 --> |
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| _| |_ |
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| <--> BUS 5 |_|10 1802 31|_| MA6 --> |
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| _| |_ |
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| <--> BUS 4 |_|11 30|_| MA5 --> |
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| _| |_ |
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| <--> BUS 3 |_|12 29|_| MA4 --> |
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| _| |_ |
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| <--> BUS 2 |_|13 28|_| MA3 --> |
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| _| |_ |
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| <--> BUS 1 |_|14 27|_| MA2 --> |
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| _| |_ |
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| <--> BUS 0 |_|15 26|_| MA1 --> |
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| _| |_ |
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| Vcc |_|16 25|_| MA0 --> |
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| _| |_ ___ |
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| <-- N2 |_|17 24|_| EF1 <-- |
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| _| |_ ___ |
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| <-- N1 |_|18 23|_| EF2 <-- |
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| _| |_ ___ |
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| <-- N0 |_|19 22|_| EF3 <-- |
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| _| |_ ___ |
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| Vss |_|20 21|_| EF4 <-- |
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| |______________________| |
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|Written by Jonathan Bowen |
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| Programming Research Group |
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| Oxford University Computing Laboratory |
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| 8-11 Keble Road |
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| Oxford OX1 3QD |
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| England |
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| Tel +44-865-273840 |
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|Created August 1981 |
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|Updated April 1985 |
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|Issue 1.3 Copyright (C) J.P.Bowen 1985|
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----------------------------------------------------------------
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----------------------------------------------------------------
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|Mnem. |Op|F|Description |Notes |
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|------+--+-+----------------------------+---------------------|
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|ADC |74|*|Add with Carry |{DF,D}=mx+D+DF |
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|ADCI i|7C|*|Add with Carry Immediate |{DF,D}=mp+D+DF,p=p+1 |
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|ADD |F4|*|Add |{DF,D}=mx+D |
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|ADI i|FC|*|Add Immediate |{DF,D}=mp+D,p=p+1 |
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|AND |F2|*|Logical AND |D={mx}&D |
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|ANI i|FA|*|Logical AND Immediate |D={mp}&D,p=p+1 |
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|B1 a|34|-|Branch if EF1 |If EF1=1 BR else NBR |
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|B2 a|35|-|Branch if EF2 |If EF2=1 BR else NBR |
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|B3 a|36|-|Branch if EF3 |If EF3=1 BR else NBR |
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|B4 a|37|-|Branch if EF4 |If EF4=1 BR else NBR |
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|BDF a|33|-|Branch if DF |If DF=1 BR else NBR |
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|BGE a|33|-|Branch if Greater or Equal |See BDF |
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|BL a|38|-|Branch if Less |See BNF BR else NBR |
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|BM a|38|-|Branch if Minus |See BNF |
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|BN1 a|3C|-|Branch if Not EF1 |If EF1=0 BR else NBR |
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|BN2 a|3D|-|Branch if Not EF2 |If EF2=0 BR else NBR |
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|BN3 a|3E|-|Branch if Not EF3 |If EF3=0 BR else NBR |
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|BN4 a|3F|-|Branch if Not EF4 |If EF4=0 BR else NBR |
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|BNF a|38|-|Branch if Not DF |If DF=0 BR else NBR |
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|BNQ a|39|-|Branch if Not Q |If Q=0 BR else NBR |
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|BNZ a|3A|-|Branch if D Not Zero |If D=1 BR else NBR |
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|BPZ a|33|-|Branch if Positive or Zero |See BDF |
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|BQ a|31|-|Branch if Q |If Q=1 BR else NBR |
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|BR a|30|-|Branch |pl=mp |
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|BZ a|32|-|Branch if D Zero |If D=0 BR else NBR |
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|DEC r|2N|-|Decrement register N |n=n-1 |
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|DIS |71|-|Disable |{X,P}=mx,x=x+1,IE=0 |
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|GHI r|9N|-|Get High register N |D=nh |
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|GLO r|8N|-|Get Low register N |D=nl |
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|IDL |00|-|Idle (wait for DMA or int.) |Bus=m0 |
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|INC r|1N|-|Increment register N |n=n+1 |
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|INP d|6N|-|Input (N=d+8=9-F) |mx=Bus,D=Bus,Nlines=d|
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|IRX |60|-|Increment register X |x=x+1 |
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|LBDF a|C3|-|Long Branch if DF |If DF=1 LBR else LNBR|
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|LBNF a|C8|-|Long Branch if Not DF |If DF=0 LBR else LNBR|
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|LBNQ a|C9|-|Long Branch if Not Q |If Q=0 LBR else LNBR |
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|LBNZ a|CA|-|Long Branch if D Not Zero |If D=1 LBR else LNBR |
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|LBQ a|C1|-|Long Branch if Q |If Q=1 LBR else LNBR |
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|LBR a|C0|-|Long Branch |p=mp |
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|LBZ a|C2|-|Long Branch if D Zero |If D=0 LBR else LNBR |
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|LDA r|4N|-|Load advance |D=mn,n=n+1 |
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|LDI i|F8|-|Load Immediate |D=mp,p=p+1 |
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|LDN r|0N|-|Load via N (except N=0) |D=mn |
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|LDX |F0|-|Load via X |D=mx |
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|LDXA |72|-|Load via X and Advance |D=mx,x=x+1 |
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|LSDF |CF|-|Long Skip if DF |If DF=1 LSKP else NOP|
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|LSIE |CC|-|Long Skip if IE |If IE=1 LSKP else NOP|
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|LSKP |C8|-|Long Skip |See NLBR |
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|LSNF |C7|-|Long Skip if Not DF |If DF=0 LSKP else NOP|
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|LSNQ |C5|-|Long Skip if Not Q |If Q=0 LSKP else NOP |
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|LSNZ |C6|-|Long Skip if D Not Zero |If D=1 LSKP else NOP |
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|LSQ |CD|-|Long Skip if Q |If Q=1 LSKP else NOP |
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|LSZ |CE|-|Long Skip if D Zero |If D=0 LSKP else NOP |
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|MARK |79|-|Push X,P to stack (T={X,P})|m2={X,P},X=P,r2=r2-1 |
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|NBR |38|-|No short Branch (see SKP) |p=p+1 |
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|NLBR a|C8|-|No Long Branch (see LSKP) |p=p+2 |
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|NOP |C4|-|No Operation |Continue |
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|OR |F1|*|Logical OR |D={mx}vD |
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|ORI i|F9|*|Logical OR Immediate |D={mp}vD,p=p+1 |
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|OUT d|6N|-|Output (N=d=1-7) |Bus=mx,x=x+1,Nlines=d|
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|PLO r|AN|-|Put Low register N |nl=D |
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|PHI r|BN|-|Put High register N |nh=D |
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|REQ |7A|-|Reset Q |Q=0 |
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|RET |70|-|Return |{X,P}=mx,x=x+1,IE=1 |
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|RSHL |7E|*|Ring Shift Left |See SHLC |
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|RSHR |76|*|Ring Shift Right |See SHRC |
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|SAV |78|-|Save |mx=T |
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|SDB |75|*|Subtract D with Borrow |{DF,D}=mx-D-DF |
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|SDBI i|7D|*|Subtract D with Borrow Imm. |{DF,D}=mp-D-DF,p=p+1 |
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|SD |F5|*|Subtract D |{DF,D}=mx-D |
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|SDI i|FD|*|Subtract D Immediate |{DF,D}=mp-D,p=p+1 |
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|SEP r|DN|-|Set P |P=N |
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|SEQ |7B|-|Set Q |Q=1 |
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|SEX r|EN|-|Set X |X=N |
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|SHL |FE|*|Shift Left |{DF,D}={DF,D,0}<- |
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|SHLC |7E|*|Shift Left with Carry |{DF,D}={DF,D}<- |
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----------------------------------------------------------------
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----------------------------------------------------------------
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|Mnem. |Op|F|Description |Notes |
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|------+--+-+----------------------------+---------------------|
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|SHR |F6|*|Shift Right |{D,DF}=->{0,D,DF} |
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|SHRC |76|*|Shift Right with Carry |{D,DF}=->{D,DF} |
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|SKP |38|-|Short Skip |See NBR |
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|SMB |77|*|Subtract Memory with Borrow |{DF,D}=D-mx-{~DF} |
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|SMBI i|7F|*|Subtract Mem with Borrow Imm|{DF,D}=D-mp-~DF,p=p+1|
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|SM |F7|*|Subtract Memory |{DF,D}=D-mx |
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|SMI i|FF|*|Subtract Memory Immediate |{DF,D}=D-mp,p=p+1 |
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|STR r|5N|-|Store via N |mn=D |
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|STXD |73|-|Store via X and Decrement |mx=D,x=x-1 |
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|XOR |F3|*|Logical Exclusive OR |D={mx}.D |
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|XRI i|FB|*|Logical Exclusive OR Imm. |D={mp}.D,p=p+1 |
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| | |-|Interrupt action |T={X,P},P=1,X=2,IE=0 |
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|------+--+-+--------------------------------------------------|
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| |??| |8-bit hexadecimal opcode |
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| |?N| |Opcode with register/device in low 4/3 bits |
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| | |-|DF flag unaffected |
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| | |*|DF flag affected |
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|-----------+--------------------------------------------------|
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| mn |Register addressing |
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| mx |Register-indirect addressing |
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| mp |Immediate addressing |
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| R( ) |Stack addressing (implied addressing) |
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|-----------+--------------------------------------------------|
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|DFB n(,n) |Define Byte |
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|DFS n |Define Storage block |
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|DFW n(,n) |Define Word |
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|-----------+--------------------------------------------------|
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| D |Data register (accumulator, 8-bit) |
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| DF |Data Flag (ALU carry, 1-bit) |
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| I |High-order instruction digit (4-bit) |
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| IE |Interrupt Enable (1-bit) |
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| N |Low-order instruction digit (4-bit) |
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| P |Designates Program Counter register (4-bit) |
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| Q |Output flip-flop (1-bit) |
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| R |1 of 16 scratchpad Registers(16-bit) |
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| T |Holds old {X,P} after interrupt (X high, 8-bit) |
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| X |Designates Data Pointer register (4-bit) |
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|-----------+--------------------------------------------------|
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| mn |Memory byte addressed by R(N) |
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| mp |Memory byte addressed by R(P) |
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| mx |Memory byte addressed by R(X) |
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| m? |Memory byte addressed by R(?) |
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| n |Short form for R(N) |
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| nh |High-order byte of R(N) |
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| nl |Low-order byte of R(N) |
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| p |Short form for R(P) |
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| pl |Low-order byte of R(P) |
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| r? |Short form for R(?) |
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| x |Short form for R(X) |
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|-----------+--------------------------------------------------|
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| R(N) |Register specified by N |
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| R(P) |Current program counter |
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| R(X) |Current data pointer |
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| R(?) |Specific register |
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|-----------+--------------------------------------------------|
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| a |Address expression |
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| d |Device number (1-7) |
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| i |Immediate expression |
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| n |Expression |
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| r |Register (hex digit or an R followed by hex digit)|
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|-----------+--------------------------------------------------|
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| + |Arithmetic addition |
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| - |Arithmetic subtraction |
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| * |Arithmetic multiplication |
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| / |Arithmetic division |
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| & |Logical AND |
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| ~ |Logical NOT |
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| v |Logical inclusive OR |
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| . |Logical exclusive OR |
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| <- |Rotate left |
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| -> |Rotate right |
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| { } |Combination of operands |
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| ? |Hexadecimal digit (0-F) |
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| --> |Input pin |
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| <-- |Output pin |
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| <--> |Input/output pin |
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----------------------------------------------------------------
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