296 lines
16 KiB
Plaintext
296 lines
16 KiB
Plaintext
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CISC : The Intel 80486 vs. The Motorola MC68040
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---------------------------------------------------
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Source : Advanced Microprocessors by Daniel Tabak
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Scribe : X-> Mike <-X - July '92
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---------------------------------------------------
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System Comparison
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Most of the space in this text is dedicated to the most recent
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advanced CISC microprocessors, the top current products within their families;
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the Intel 80486 and the Motorola MC68040. They both belong to the latest
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1.2 million transistors per chip generation. It therefore makes sense
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to compare the two. It would be unfair to compare the NS32532 with them,
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since the NS32532 belongs to an earlier generation and it is not in the same
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class as the 80486 and MC68040.
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A selection of points of comparison between the 80486 and the MC68040
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is listed in Table 1.1. Looking carefully at the table, one can perceive
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only a single line indentically marked in both columns: both chips have an
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on-chip FPU, conforming to the IEEE 754-1985 standard. All other data are
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different, although quite close in some instances. The points of difference
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between the 80486 and the MC68040 will be discussed next in some detail.
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Table 1.1 Comparison of Intel 80486 and Motorola MC68040
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-------------------------------------------------------------------------------
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Feature Intel 80486 Motorola MC68040
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-------------------------------------------------------------------------------
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FPU on Chip Yes (IEEE) Yes (IEEE)
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CPU General-Purpose 32-bit Registers 8 16; 8 Data/8 Address
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FPU 80-bit Registers 8 (stack) 8
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MMU on Chip Yes Yes; Dual: Data, Code
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Cache on Chip 8k Mixed 4k Data + 4k Code
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Segmentation Yes No
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Paging Yes; 4k/page Yes; 4k or 8k/page
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TLB (or ATC) size 32 entries 64 entries in each:
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Data, Code ATC
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Levels of protection 4 2
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Instruction pipeline stages 5 6
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Pins 168 179
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-------------------------------------------------------------------------------
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CPU General-Purpose Registers
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Both systems have 32-bit general-purpose registers; the 80486 has 8,
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while the 68040 has double that number, namely 16. There are advantages
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(and disadvantages) to having a large register file. The register file of
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the 80486 is definitely too small to avail itself to the advantages. This
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is particularly exacerbated by the fact that the CPU registers of the 80486
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are not really quite as general purpose as one might wish. In fact, all of
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them are dedicated to certain special tasks, such as:
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EAX, EDX Dedicated to multiplication/division operations
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EDX Dedicated to some I/O operations
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EBX, EBP Dedicated to serve as base registers for some addressing modes
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ECX Dedicated to serve as a counter in LOOP instructions
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ESP Dedicated to serve as a stack pointer
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ESI, EDI Dedicated to serve as pointers in string instructions and as
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index registers in some addressing modes
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On the other hand, on the MC68040 the eight 32-bit data registers D0 to D7
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are genuinely general purpose without any restrictions or specific tasks
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imposed on them. Of the eight 32-bit address registers A0 to A7, only A7
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is dedicated as a stack pointer. The user is free to use the other seven
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resgisters A0 to A6 in any possible way.
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From the point of view of the CPU register file, the MC68040 has a
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very clear advantage. It is much better equipped to retain intermediate
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results during a program run, thus reducing CPU-memory traffic. From this
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standpoint, the MC68040 even has a slight edge over the VAX architecture.
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The VAX (any VAX model) also has sixteen 32-bit general-purpose registers.
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However, only 12 of those (as opposed to the 68040's 15) can be used freely
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by the programmer. Of the four VAX dedicated registers, one is used as a
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program counter and another as a stack pointer. The program counter is
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completely separate on both the MC68040 and the 80486 and is not included in
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the general-purpose registers.
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FPU General-Purpose Registers
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Both systems have eight 80-bit registers, providing a large range for
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floating-point number representation and a high level of precision. The only
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differnce between the two is that the 80486 FPU registers are organized as a
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stack, while those of the MC68040 are accessed directly, as its integer CPU
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registers. Because of the stack organization the 80486 might have a slight
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edge from the standpoint of compiler generation (for that part of the compiler
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dealing with floating-point operations).
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MMU on Chip
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The 80486 has a regular MMU on chip for the control and management of
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its memory. The MC68040 has two MMUs: one for code and one for data. This
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duality, supported by a separate operand data bus, allows the control unit to
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handle instruction and operand fetching simultaneously in parallel and enhances
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the handling of the instruction pipeline. Of course, the external bus leading
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to the off-chip main memory is single (32-bit data, 32-bit address), and it is
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shared by instructions and data operands. With a reasonable on-chip cache hit
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ratio, the off-chip bus would be used less often.
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Cache on Chip
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The total on-chip cache of both systems is 8 kbytes. Interestingly
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enough, they have the same parameters: both are four-way set-associative with
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16 bytes per line. The difference is that while the 80486 on-chip 8k cache
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is mixed, storing both code and data the MC68040 cache is subdivided into two
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equal parts: a 4-kbyte data cache and a 4-kbyte code cache. Each cache is
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controlled by the respective MMU, mentioned above. The advantage, as in the
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MMU case, is the provision of two parallel paths for code and data, resulting
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in an overall speedup of operation.
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Segmentation
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The Intel 80x86 family implements segmentation, while the M68000 family
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does not. The earlier Intel systems (8086, 80286) were plagued with the upper
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64-kbyte segment size limit, starting with the 80386 and so on, the segment sizecan be made as high as 4 Gbytes (maximum size of the physical memory),
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effectively removing the segmentation feature by the decision of the user.
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Therefore, as far as segmentation is concerned, the 80486 and MC68040 are
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comparable. The 80486 has some edge, since it allows the user to implement
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segmentation if needed and avail oneself to its advantages.
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Paging
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The MMUs of both systems feature paged virtual memory management.
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The 80486 offers a single standard page size of 4 kbytes. This page size
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is implemented in many other systems. With a 4-kbyte page size, one can
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arrange an address mapping where the page directory and the page tables also
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have the standard page size of 4 kbytes (1024 = 2^10 entries, 4 bytes each).
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Thus, the page directory and the page tables can be treated as entire pages
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and placed within page frames in the memory. This results in reduced
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complexity in the MMU hardware and in the OS software, one of whose tasks is
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to support the management of virtual memory. The MC68040 offers two page
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sizes, selectable by the user: 4 kbytes and 8 kbytes. This tends to
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complicate the MMU logic and the OS. It is a good thing that Motorola got
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rid of the other page size options available with its MC68851 paged MMU:
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8 sizes ranging from 256 bytes to 32 kbytes, stepped by a factor of 2. On the
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other hand, the 8-kbyte per page option could be useful to a programmer dealing
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with large modules of code exceeding 4 kbytes.
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TLB (or ATC) Size
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The 80486 MMU has a 32-entry TLB. With a 4-kbyte page it covers
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32 x 4 kbytes = 128 kbytes of memory. The MC68040 offers much more. The TLB
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is called address translation cache (ATC) by Motorola, but it does the same:
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it translates virtual into physical addresses. The name given by Motorola is
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simpler to perceive, although the TLB term is predominately used in the
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computer literature. Each of the two MC68040 MMUs has a 64-entry ATC, for a
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total of 128 entries on the chip. For a 4-kbyte page, a total of 128 x 4
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kbytes = 512 kbytes of memory is covered (4 times that of the 80486), and for
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an 8-kbyte page, 1 Mbyte (8 times that of 80486). In this case, a strong
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advantage of the MC68040 is obvious. Since the ATCs encompass much more
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memory, the ATC miss probability is considerably smaller. Thus, less time
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will be wasted in accessing page tables in memory, resulting in faster overall
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operation.
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Levels of Protection
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The 80486 offers four levels of protection, while the MC68040 has only
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two - the supervisor and user, as does the whole M68000 family. While the
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protection mechanism of the 80486 is much more sophisticated and, with the
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segmentation encapsulation of information, offers more reliable protection,
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it also results in more complicated on-chip logic. More time is taken up with
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protection checks on the 80486.
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Instruction Pipeline Stages
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The 80486 instruction pipeline has five stages, while that of the
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MC68040 has six. This means that the 80486 pipeline can handle five
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instructions simultaneously and the MC68040 can handle six. This certainly
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gives an edge in favor of the MC68040, although its MMU-cache-internal buses
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duality is a much stronger contributor to its enhanced speed of operation.
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The above comments are valid if the instructions are executed sequentially,
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without any taken branches. In the case of the taken branch, the subsequent
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prefetched instructions are flushed from the pipeline hardware. Neither
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the 80486 nor the MC68040 employ the delayed branch feature, as do most of
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the RISC-type systems. The MC68040 designers have investigated the possibilityof featuring a delayed branch or other techniques to alleviate the problem of
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lost cycles in case of a flushed pipeline. After a number of simulations,
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they came to the conclusion that the gain in performance was not worth the
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extra hardware expenditure incurred in the implementation of any of the methods
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considered. In RISC-type systems, on the other hand, due to reduced control
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circuitry there is extra space for features such as the delayed branch which
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alleviates the pipeline management problem in case of a taken branch. Indeed,
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Intel's RISC 80860 and Motorola's RISC M88000 both implement the delayed branch
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technique as an option, selectable by the user.
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Performance Benchmarks
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Dhrystone Benchmark Version 2.1 (Integer Performance Test -- ALU)
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-----------------------------------------------------------------------------
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System Results - Kdhrystones/s Relative
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-----------------------------------------------------------------------------
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VAX 11/780 1.6 1.0
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Motorola MC68030 (50 Mhz,1ws) 20.0 12.5
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Intel 80486 (25 Mhz) 24.0 15.0
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SPARC (25 Mhz) 27.0 16.8
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Motorola M88000 (20 Mhz) 33.3 20.1
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MIPS M/2000, R3000 (25 Mhz) 39.4 23.8
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Motorola MC68040 (25 Mhz) 40.0 24.3
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Intel 80860 (33.3 Mhz) 67.3 40.6
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-----------------------------------------------------------------------------
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As one can see, the MC68040 Dhrystone integer performance considerably
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exceeds that of the 80486. It should also be noted that the MC68040
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outperforms its predecessor MC68030 by a factor of 2, while the MC68030
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operates at a double frequency.
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Linpack Benchmark (Double-Precision, 100x100) (F-P Performance Test -- FPU)
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-----------------------------------------------------------------------------
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System Results - MFLOPS
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-----------------------------------------------------------------------------
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VAX 11/780 0.14
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NS32532 + NS32381 0.17
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Intel 80386 + 80387 (20 Mhz) 0.20
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VAX 8600 0.49
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Intel 80486 (25 Mhz) 1.0
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Motorola M88000 (20 Mhz) 1.2
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Sun SPARCstation 1 1.3
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Decstation 3100 (MIPS R2000) 1.6
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Sun 4/200 (SPARC) 1.6
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Am29000 (25 Mhz) 1.71
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IBM 3081 2.1
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Motorola MC68040 (25 Mhz) 3.0
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R3000/R3010 (25 Mhz) 3.9
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Intel 80860 4.5
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RS/6000 (25 Mhz) 10.9
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Cray 1S 12.0
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Cray X-MP 56.0
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-----------------------------------------------------------------------------
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Here, the MC68040 outperforms the 80486 by a factor of 3. This
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performance ratio is well supported by the discussion given for the data
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in Table 1.1.
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The fact that more RISC-type processors, tested above, outperform the
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80486 CISC should not escape notice either. This is particularly significant
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for floating-point performance where the 80486 has an on-chip FPU, while the
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R3000 and the SPARC use off-chip coprocessors.
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A comparison of memory access clock cycles needed for the execution of
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ADD instructions is reported in the following:
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Memory Access Clock Counts
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-----------------------------------------------------------------------------
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Source Destination MC68040 80486 M88000
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-----------------------------------------------------------------------------
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ADD reg reg 1 1 1
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ADD mem reg (cache hit) 1 2 3*
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ADD reg mem (cache hit) 1 1 3*
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ADD mem reg (cache miss) 3 4 15*
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-----------------------------------------------------------------------------
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--"reg" represents a CPU register and "mem" represents a location in memory.
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*Includes time to load register plus one clock for the ADD operation.
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The superior performance of the MC68040 fits the discussion given
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earlier in this text. It should also be noted that both the MC68040 and
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80486 have an on-chip cache, while the M88000 cache is on a separate CMMU
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chip (MC88200).
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It should be noted that all of the above comparisons were conducted
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with artificial benchmark programs such as Dhrystone. It is quite possible
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that for some "real-life" programs the performance ordering might be quite
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different. It is no accident that when company A conducts benchmark
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experiments, its products come out ahead of others. It is quite possible
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that when another company, say B, publishes its own benchmark results, the
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performance ordering may look different. Therefore, the sample of benchmark
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comparison results presented should be regarded as a tentative indication.
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They are certainly not conclusive.
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<*><*><*><*><*><*><*><*><*><*><*><*><*><*><*><*><*><*><*><*><*><*><*><*><*>
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<*> <*>
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<*> >>> THIS TEXTFILE PASSED THROUGH IMAGINE BBS ++46-42-135505 <<< <*>
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<*> """"""""""""""""""""""""""""""""""""""""""""""""""""""" <*>
|
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|
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<*><*><*><*><*><*><*><*><*><*><*><*><*><*><*><*><*><*><*><*><*><*><*><*><*>
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<<3C><>S<EFBFBD>C<EFBFBD>O<EFBFBD>O<EFBFBD>P<EFBFBD>E<EFBFBD>X<EFBFBD><58><EFBFBD>S<EFBFBD>W<EFBFBD>E<EFBFBD>D<EFBFBD>E<EFBFBD>N<EFBFBD><4E><EFBFBD>H<EFBFBD>E<EFBFBD>A<EFBFBD>D<EFBFBD>Q<EFBFBD>U<EFBFBD>A<EFBFBD>R<EFBFBD>T<EFBFBD>E<EFBFBD>R<EFBFBD><52>>
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